NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 256

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 135. Data Values for Slave Read Registers (Sheet 2 of 2)
5.19.8.2.1 Behavioral Notes
5.19.8.3 Format of Host Notify Command
Intel
DS
256
Warning:The external microcontroller is responsible to make sure that it does not read
®
6300ESB I/O Controller Hub
Note: An external microcontroller must not attempt to access the Intel
Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any
the contents of the various message registers until they have been written by
the system processor. The Intel
with any new value received. A race condition is possible where the new value
is being written to the register just at the time it is being read. The Intel
6300ESB ICH will not attempt to cover this race condition (i.e., unpredictable
results).
According to SMBus protocol, Read and Write messages always begin with a Start bit -
Address - Write bit sequence. When the Intel
matches the value in the Receive Slave Address register, it will assume that the
protocol is always followed and ignore the Write bit (bit 9) and signal an Acknowledge
during bit 10 (See
Read occurs (which is illegal for SMBus Read or Write protocol), and the address
matches the Intel
grab the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start - Address -
Read sequence beginning at bit 20 (See
matches the Intel
protocol is followed, ignore bit 28, and proceed with the Slave Read cycle.
SMBus Slave logic until at least 1 second after both RTCRST# and RSMRST# are
deasserted (high).
The Intel
specified in the SMBus 2.0 specification. The host address for this command is fixed to
0001000b. When the Intel
host notify command which has not been serviced yet by the host software (as
indicated by the HOST_NOTIFY_STS bit), it will NACK following the host address byte of
the protocol. This allows the host to communicate non-acceptance to the master and
retain the host notify address and data values for the previous cycle until host software
completely services the interrupt.
necessary reads of the address and data registers.
Table 136
Registe
9 – FFh
5
6
7
8
r
®
shows the Host Notify format.
7:3
7:0
7:0
7:0
7:0
Bit
6300ESB ICH tracks and responds to the standard Host Notify command as
s
Reserved
Contents of the Message 1 register. See
TCO_MESSAGE2
Contents of the Message 2 register. See
TCO_MESSAGE2
Contents of the WDSTATUS register. See
OEh: TCO_WDSTATUS—TCO2 Control
Reserved
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®
Table 131
6300ESB ICH’s Slave Address, the Intel
6300ESB ICH’s Receive Slave Address, it will assume that the
®
6300ESB ICH already has data for a previously-received
and
Registers”.
Registers”.
Table
®
6300ESB ICH will overwrite the old value
134). In other words, when a Start - Address -
Table
®
Description
134). Once again, when the Address
6300ESB ICH detects that the address
Register”.
Section 8.9.10, “TCO_MESSAGE1 and
Section 8.9.10, “TCO_MESSAGE1 and
Section 8.9.11, “Offset TCOBASE +
®
6300ESB ICH will still
Order Number: 300641-004US
®
6300ESB ICH’s
Intel
®
6300ESB ICH—5
November 2007
®