NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 198

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 88.
Intel
DS
198
®
6300ESB I/O Controller Hub
TD Control and Status (Sheet 1 of 3)
31:30
28:27
Bit
29
26
25
24
Reserved.
Short Packet Detect (SPD): When a packet has this bit set to 1 and the packet is an
input packet, is in a queue; and successfully completes with an actual length less than
the maximum length then the TD is marked inactive, the Queue Header is not updated
and the USBINT status bit (Status Register) is set at the end of the frame. In addition,
when the interrupt is enabled, the interrupt will be sent at the end of the frame.
Note that any error (e.g., babble or FIFO error) prevents the short packet from being
reported. The behavior is undefined when this bit is set with output packets or packets
outside of queues.
0 = Disable
1 = Enable
Error Counter (C_ERR): This field is a 2-bit down counter that keeps track of the
number of Errors detected while executing this TD. When this field is programmed with
a non zero value during setup, the Intel
writes it back to the TD when the transaction fails. When the counter counts from one
to zero, the Intel
status bit for the error that caused the transition to zero in the TD. An interrupt will be
generated to Host Controller Driver (HCD) when the decrement to zero was caused by
Data Buffer error, Bit stuff error, or when enabled, a CRC or Timeout error. When HCD
programs this field to zero during setup, the Intel
for this TD and there will be no limit on the retries of this TD.
Bits[28:27]Interrupt After
00
01
10
11
Error
CRC Error
Timeout Error
NAK Received
Babble Detected No
†
decremented.
Low Speed Device (LS): This bit indicates that the target device (USB data source or
sink) is a low speed device, running at 1.5 Mb/s, instead of at full speed (12 Mb/s).
There are special restrictions on schedule placement for low speed TDs. When an Intel
6300ESB ICH root hub port is connected to a full speed device and this bit is set to a 1
for a low speed transaction, the Intel
on that port before sending the PID. No preamble is sent when a Intel
root hub port is connected to a low speed device.
0 = Full Speed Device
1 = Low Speed Device
Isochronous Select (IOS): The field specifies the type of the data structure. When
this bit is set to a 1, then the TD is an isochronous transfer. Isochronous TDs are always
marked inactive by the hardware after execution, regardless of the results of the
transaction.
0 = Non-isochronous Transfer Descriptor
1 = Isochronous Transfer Descriptor
Interrupt on Complete (IOC): This specifies that the Intel
issue an interrupt on completion of the frame in which this Transfer Descriptor is
executed. Even when the Active bit in the TD is already cleared when the TD is fetched
(no transaction will occur on USB), an IOC interrupt is generated at the end of the
frame.
1 = Issue IOC
Detection of Babble or Stall automatically deactivates the TD. Thus, count is not
No Error Limit
1 Error
2 Errors
3 Errors
Decrement Counter
®
Yes
Yes
No
6300ESB ICH marks the TD inactive, sets the “STALLED” and error
†
®
Description
6300ESB ICH sends out a low speed preamble
®
Error
Data Buffer Error
Stalled
Bit stuff Error
6300ESB ICH decrements the count and
®
6300ESB ICH will not count errors
®
Order Number: 300641-004US
Decrement Counter
6300ESB ICH should
Intel
Yes
No
Yes
®
®
1
6300ESB ICH
6300ESB ICH—5
November 2007
®