NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 223

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
Table 108. EHC Resets
5.18.3
November 2007
Order Number: 300641-004US
®
6300ESB ICH
When the detailed register descriptions give exceptions to these rules, those exceptions
override these rules. This summary is provided to help explain the reasons for the reset
policies.
Data Structures in Main Memory
See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification
for Universal Serial Bus, Revision 0.96.
HCRESET bit
set
Software writes
the Device
Power State
from D3 hot
(11b) to D0
(00b).
Reset
Memory space
registers except
Structural Parameters
(which is written by
BIOS).
Core well registers
(except BIOS-
programmed
registers).
Does Reset
Configuration
registers
Suspend well
registers; BIOS-
programmed core
well registers
Does not Reset
The HCRESET must only
affect registers that the EHCI
driver controls. PCI
Configuration space and
BIOS-programmed
parameters cannot be reset.
See
CAPLENGTH + 00 - 03h: USB
EHCI CMD—USB EHCI
Command Register”
information regarding offset
00h, bit 1.
The D3-to-D0 transition must
not cause wake information
(suspend well) to be lost. It
also must not clear BIOS-
programmed registers
because BIOS may not be
invoked following the D3-to-
D0 transition.
See
54 - 55h: Power Management
Control/Status”
information.
Intel
Section 11.2.2.1, “Offset
Section 11.1.17, “Offset
®
6300ESB I/O Controller Hub
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