NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 561

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

13—Intel
13.1.18 Offset 3Dh: INTR_PN—Interrupt Pin Register
13.1.19 Offset 40h: PCID—Programmable Codec ID
November 2007
Order Number: 300641-004US
Bits
Bits
Default Value:
Default Value:
7:3
2:0
7:4
3:2
1:0
Table 477. Offset 3Dh: INTR_PN—Interrupt Pin Register (Audio—D31:F5)
Table 478. Offset 40h: PCID—Programmable Codec ID Register (Audio—
Lockable:
Lockable:
Note: This register indicates which PCI interrupt pin is used for the AC’97 module interrupt.
Note: This register is used to specify the ID for the secondary and tertiary codecs for I/O
Note: The value in this register must only be modified prior to any AC’97 codec accesses.
Device:
Device:
®
AC'97 Interrupt Routing
Offset:
Offset:
Tertiary Codec ID (TID)
Secondary Codec ID
6300ESB ICH
(Audio—D31:F5)
The AC’97 interrupt is internally OR’d to the interrupt controller with the PIRQB# signal.
Register
(Audio—D31:F5)
accesses. This register is not affected by the D3
D31:F5)
Reserved
Reserved
(SCID)
31
3Dh
3Dh
No
Name
31
40h
00h
No
Name
Reserved.
Hardwired to 010b to select PIRQB#.
Reserved.
These bits define the encoded ID that is used to address the
tertiary codec I/O space. Bit ’1’ is the first bit sent and Bit ’0’
is the second bit sent on AC_SDATA_OUT during slot 0.
These two bits define the encoded ID that is used to address
the secondary codec I/O space. The two bits are the ID that
will be placed on slot 0, bits ’0’ and ‘1’, upon an I/O access to
the secondary codec. Bit ’1’ is the first bit sent and bit ’0’ is
the second bit sent on AC_SDATA_OUT during slot 0.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
HOT
5
Read-Only
8-bit
Core
5
Read/Write
8-bit
Core
to D0 transition.
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
R/W
RO
561
DS