NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 712
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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Table 640. Interrupt Enable Register (IER)
19.5.1.3.4 Interrupt Identification Register (IIR)
Intel
DS
712
®
6300ESB I/O Controller Hub
In order to minimize software overhead during data character transfers, the UART
prioritizes interrupts into four levels (listed in
Interrupt Identification Register. The Interrupt Identification Register (IIR) stores
information indicating that a prioritized interrupt is pending and the source of that
interrupt.
Interrupt Enable Register
IER
read/write
Bit Number
7:6
5
4
3
2
1
0
Bit Mnemonic
RTOIE
RAVIE
RSVD
COMP
RLSE
MIE
TIE
Address:
Reset State:
Access:
RSVD = 0
Compatibility Enable:
0 = Bit 0 of this register also controls RTOIE and bit 4 is RSVD.
1 = Bit 4 of this register controls RTOIE.
NOTE: The use of bit 5 is different from the register definition
Receiver Time Out Interrupt Enable:
0 = Receiver data Time out interrupt disabled.
1 = Receiver data Time out interrupt enabled.
NOTE: The use of bit 4 is different from the register definition
Modem Interrupt Enable:
0 = Modem Status interrupt disabled.
1 = Modem Status interrupt enabled.
Receiver Line Status Interrupt Enable:
0 = Receiver Line Status interrupt disabled.
1 = Receiver Line Status interrupt enabled.
Transmit Data request Interrupt Enable:
0 = Transmit FIFO Data Request interrupt disabled.
1 = Transmit FIFO Data Request interrupt enabled.
Receiver Data Available Interrupt Enable:
When BIT 5 = 1
0 = Receiver Data Available (Trigger level reached) interrupt
disabled.
1 = Receiver Data Available (Trigger level reached) interrupt
enabled.
When BIT 5 = ’0’ the following additional functionality is used.
0 = Receiver data Time Out Interrupt also disabled.
1 = Receiver data Time Out Interrupt enabled.
of the 16550. The 16550 has this bit always set to 0.
of the 16550. The 16550 has this bit always set to 0.
Table
Base + 01H (DLAB=0)
00H
8-bit
641) and records these in the
Function
Order Number: 300641-004US
Intel
®
6300ESB ICH—19
November 2007
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