NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 421

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.9.7
Table 307. TCO2_STS—TCO2 Status Register
November 2007
Order Number: 300641-004US
15:5
Bits
Default Value:
I/O Address:
4
3
2
1
0
Lockable:
®
Device:
SMLINK_SLV_SMI_STS
6300ESB ICH
INTRD_DET: Intruder
SECOND_TO_STS
BOOT_STS:
BAD_BIOS
TCO2_STS—TCO2 Status Register
Reserved
Detect
31
TCOBASE +06h
0000h
No
Name
Reserved.
SMLink Slave SMI Status (Allow the software to go directly
into pre-determined sleep state. This avoids race conditions.
0 = The bit is reset by RSMRST#, but not due to the PCI
1 = The Intel
This bit is set by the Intel
on the first BIOS read (i.e., the BIOS is bad). Intel
ICH clears this bit to 0 if the first BIOS read is not FFh. This is
detected when the initial read returns FFh from the FWH. This
bit is not intended to be read by the BIOS or software. It is
only used for sending the TCO/Heartbeat messages to an
External LAN Controller. Reads to this bit always return 0 and
writes have no effect.
0 = Cleared by the Intel
1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1
0 = This bit is cleared by writing a 1 to the bit position or by a
1 = The Intel
0 = This bit is only cleared by writing a 1 to the bit position,
1 = Set by the Intel
Reset associated with exit from S3-S5 states.
receives the SMI message on the SMLink's Slave
Interface. Software clears the bit by writing a 1 to this bit
position.
or by software writing a 1 to this bit. Note that software
should first clear the SECOND_TO_STS bit before writing
a 1 to clear the BOOT_STS bit.
and the processor has not fetched the first instruction.
RSMRST#.
that the TCO timer timed out a second time (probably
due to system lock). When this bit is set and the
NO_REBOOT configuration bit is 0, then the Intel
6300ESB ICH will reboot the system after the second
timeout. The reboot is done by asserting PXPCIRST#.
or by RTCRST# assertion.
intrusion was detected. This bit is set even when the
system is in G3 state.
®
®
6300ESB ICH sets this bit to 1 when it
6300ESB ICH sets this bit to a 1 to indicate
®
6300ESB ICH to indicate that an
Power Well:
®
Description
®
Attribute:
Function:
6300ESB ICH based on RSMRST#
6300ESB ICH when it detects FFh
Size:
0
Read-Only, Read/Write Clear
16-bit
Resume (Except Bit 0, in RTC)
Intel
®
6300ESB
®
®
6300ESB I/O Controller Hub
Access
R/WC
R/WC
R/W
421
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