NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 172

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.12.4
5.12.4.1 Overview
5.12.4.1.1 TCO Compatible Mode
Table 78.
Intel
DS
172
®
6300ESB I/O Controller Hub
Note: A system that has locked up and cannot be restarted with a power button press is
Heartbeat and Event Reporting through SMLink/
SMbus
SMLink signals are implemented on the Intel
compatible mode. Heartbeat and event reporting are accomplished via the SMLink
signals.
The Intel
messages to a network management console without the aid of the system processor.
This is crucial in cases where the processor is malfunctioning or cannot function due to
being in a low-power state.
assumed to have broken hardware (bad power supply, short circuit on some bus, etc.),
and is beyond the Intel
The basic scheme is for the Intel
SMLink
I/F to the LAN. Upon receiving the SMLink message, the LAN has a prepared Ethernet
message that it may send to a network management console. The prepared message is
stored in a non-volatile memory connected directly to the LAN.
Messages will be sent by the Intel
event has occurred (see
Heartbeat). The Event and Heartbeat messages will have exactly the same form.
Event Transitions that Cause Messages
Whenever an event occurs that causes the Intel
message, it will increment its SEQ[3:0] field. For Heartbeat messages, the sequence
number will not increment.
INTRUDER# pin
THRM# pin
Watchdog Timer Expired
SEND_NOW bit
GPIO[11]/SMBALERT#
pin
CPU_PWR_FLR
NOTE: The GPIO[11]/SMBALERT# pin will trigger an event message (when enabled by the
GPIO11_ALERT_DISABLE bit) regardless of whether it is configured as a GPI or not.
®
Event
6300ESB ICH may function directly with a LAN Controller to report
®
Table
6300ESB ICH’s recovery mechanisms.
Assertion
Yes
Yes
Yes
Yes
Yes
Yes
?
78), or they will be sent periodically (also known as a
®
®
6300ESB ICH to send specific messages through the
6300ESB ICH to a LAN either because a specific
Deassertion
No (NA)
Yes
Yes
No
NA
No
?
®
6300ESB ICH ICH to support TCO
®
6300ESB ICH to send a new
Must be in “heartbeat mode” (G1 or
hung G0).
Must be in “heartbeat mode”. Note
that the THRM# pin is isolated when
the core power is off, thus preventing
this event in S3-S5. Also, the THRM#
pin is sampled with the PCI clock,
which means that THRM# transitions
cannot be detected in S1-M.
“Heartbeat mode” entered
Occurs in G0
Must be in “heartbeat mode” (G1 or
hung G0).
“HeartBeat mode” entered {Intel
6300ESB ICH DCN36}.
Order Number: 300641-004US
Comments
Intel
®
6300ESB ICH—5
November 2007
®