NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 544
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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12.2.12 Offset 0Dh: AUX_CTL—Auxiliary Control Register
12.2.13 Offset 0Eh: SMLINK_PIN_CTL—SMLink Pin Control
Intel
DS
544
Bits
Bits
Default Value:
Default Value:
7:2
7:3
1
0
2
1
0
®
Table 451. Offset 0Dh: AUX_CTL—Auxiliary Control Register
Table 452. Offset 0Eh: SMLINK_PIN_CTL—SMLink Pin Control Register
6300ESB I/O Controller Hub
Lockable:
Note: This register is in the resume well and is reset by RSMRST#.
Device:
Device:
Offset:
Offset:
Enable 32-byte Buffer
Automatically Append
SMLINK1_CUR_STS
SMLINK0_CUR_STS
SMLINK_CLK_CTL
CRC (AAC)
Register
Reserved
Reserved
(E32B)
31
0Dh
00h
No
Name
31
0Eh
See Note
Name
Reserved.
When set, the Host Block Data register is a pointer into a
32-byte buffer, as opposed to a single register. This enables
the block commands to transfer or receive up to 32 bytes
before the Intel
When set, the Intel
the CRC. This bit must not be changed during SMBus
transactions, or undetermined behavior will result
Reserved.
This Read/Write bit has a default of 1.
0 = The Intel
1 = The SMLINK[0] pin is not overdriven low. The other
This read-only bit has a default value that is dependent on an
external signal level. This pin returns the value on the
SMLINK[1] pin. It will be ’1’ to indicate high, ’0’ to indicate
low. This allows software to read the current state of the pin.
This read-only bit has a default value that is dependent on an
external signal level. This pin returns the value on the
SMLINK[0] pin. It will be ’1’ to indicate high, ’0’ to indicate
low. This allows software to read the current state of the pin.
low, independent of what the other SMLINK logic would
otherwise indicate for the SMLINK[0] pin.
SMLINK logic controls the state of the pin.
®
6300ESB ICH will drive the SMLINK[0] pin
®
6300ESB ICH generates an interrupt.
®
6300ESB ICH will automatically append
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
3
Read/Write
8-bit
Resume
3
Read/Write
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—12
November 2007
Access
Access
R/W
R/W
R/W
RO
RO
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