NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 505

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11—Intel
11.2.1.2 Offset 02 - 03h: HCIVERSION—Host Controller Interface
Table 409. Offset 02 - 03h: HCIVERSION—Host Controller Interface Version
11.2.1.3 Offset 04 - 07h: HCSPARAMS—Host Controller Structural
Table 410. Offset 04 - 07h: HCSPARAMS—Host Controller Structural Parameters
November 2007
Order Number: 300641-004US
15:0
31:2
23:2
19:1
Bits
Bits
Default Value:
Default Value:
16
4
0
7
Note: This register is reset by a suspend well reset and not a D3-to-D0 reset or HCRESET.
Note: This register is writable when the WRT_RDONLY bit is set.
Device:
Host Controller Interface
Device:
®
Offset:
Offset:
6300ESB ICH
Debug Port Number
Version Number
Version Number
Number
Parameters
(Sheet 1 of 2)
Reserved
Reserved
Reserved
(DP_N)
29
02 - 03h
0100h
Name
29
04-07h
00102204h
Name
This is a two-byte register containing a BCD encoding of the
version number of interface that this host controller interface
conforms.
Reserved. Default = 0h.
Hardwired to 1h, indicating that the Debug Port is on the
lowest numbered port on the Intel
Reserved.
Reserved. Hardwired to 0.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
®
6300ESB ICH.
7
Read-Only
16-bit
7
Read/Write-Special
32-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
RO
RO
505
DS