NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 342

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.1.35
Table 215. Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC I/F—
Intel
DS
342
Bits
Default Value:
7:4
3
2
1
0
®
6300ESB I/O Controller Hub
Lockable:
Note: This register determines which memory ranges will be decoded on the PCI bus and
Device:
Offset:
FWH_70_EN
FWH_60_EN
FWH_50_EN
FWH_40_EN
Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2
Register (LPC I/F—D31:F0)
forwarded to the FWH. The Intel
unless POS_DEC_EN is set to 1.
D31:F0)
Reserved
31
F0h
0Fh
No
Name
Reserved.
Enables decoding two 1M FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
Enables decoding two 1M FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
Enables decoding two 1M FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
Enables decoding two 1M FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FF70 0000h - FF7F FFFFh
FF30 0000h - FF3F FFFFh
FF60 0000h - FF6F FFFFh
FF20 0000h - FF2F FFFFh
FF50 0000h - FF5F FFFFh
FF10 0000h - FF1F FFFFh
FF40 0000h - FF4F FFFFh
FF00 0000h - FF0F FFFFh
®
6300ESB ICH will subtractively decode cycles on PCI
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
8-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W
R/W
R/W