NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 621

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

16—Intel
16.4.7
Table 542. Offset 08h: RID—Revision Identification Register
November 2007
Order Number: 300641-004US
10:9
Bits
Default Value:
4:0
15
14
13
12
11
8
7
6
5
Lockable:
Note: Refer to the Intel
Device:
DEVT - DEVSEL# Timing
®
Offset:
SSE - Signaled System
RMA - Received Master
STA - Signaled Target-
RTA - Received Target
DPE - Detected Parity
UDF - User Definable
6300ESB ICH
Fast Back-to-Back
Data Parity Error
66 MHz Capable
Abort Status
Offset 08h: RID—Revision Identification Register
to-date value of the Revision ID.
Reserved
Detected
Features
Capable
29
08h
See Note
No
Name
Status
Abort
Abort
Error
Error
®
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
This bit is set when the function is targeted with a transaction
that Intel
Software resets STA to ’0’ by writing a ’1’ to this bit location.
This two-bit field defines the timing for DEVSEL# assertion.
These read-only bits indicate the Intel
DEVSEL# timing when performing a positive decode.
The Intel
time.
Reserved as ‘0’.
Reserved as ‘1’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved.
6300ESB I/O Controller Hub Specification Update for the most up-
®
®
6300ESB ICH generates DEVSEL# with medium
6300ESB ICH terminates with a target abort.
Power Well:
Description
Attribute:
Function:
Size:
4
Read-Only
16-bit
Core
®
6300ESB ICH’s
Intel
®
6300ESB I/O Controller Hub
Access
R/WC
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
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