NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 237

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.19
5.19.1
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Debug software may attempt to use the debug port after setting the OWNER_CNT bit in
the Control/Status Register,
offset 00h, bit 30, and the Current Connect Status bit in the appropriate (See
Determining the Debug Port) PORTSC register is set. See
Port N Status and Control”
Status bit is not set, then debug software may choose to terminate or it may choose to
wait until a device is connected.
When a device is connected to the port, then debug software must reset/enable the
port. Debug software does this by setting and then clearing the Port Reset bit the
PORTSC register. To ensure a successful reset, debug software should wait at least 50
ms before clearing the Port Reset bit. Due to possible delays, this bit may not change to
zero immediately; reset is complete when this bit reads as zero. Software must not
continue until this bit reads zero.
When a high-speed device is attached, the EHCI will automatically set the Port
Enabled/Disabled bit in the PORTSC register and the debug software may proceed.
Debug software should set the ENABLED_CNT bit in the Debug Port Control/Status
register, and then reset (clear) the Port Enabled/Disabled bit in the PORTSC register (so
that the system host controller driver doesn't see an enabled port when it is first
loaded).
Debug Software Startup with Initialized EHCI
Debug software may attempt to use the debug port when the Current Connect Status
bit in the appropriate (See Determining the Debug Port) PORTSC register is set. When
the Current Connect Status bit is not set, then debug software may choose to
terminate or it may choose to wait until a device is connected.
When a device is connected, then debug software must set the OWNER_CNT bit and
then the ENABLED_CNT bit in the Debug Port Control/Status register. See
Section 11.2.3.1, “Offset 00h: Control/Status Register”
00h, bits 30 and 28.
Determining Debug Peripheral Presence
After enabling the debug port functionality, debug software may determine when a
debug peripheral is attached by attempting to send data to the debug peripheral. When
all attempts result in an error (Exception bits in the Debug Port Control/Status register
indicates a Transaction Error), the attached device is not a debug peripheral. See
Section 11.2.3.1, “Offset 00h: Control/Status Register”
00h, bits [9:7]. When the debug port peripheral is not present, then debug software
may choose to terminate or it may choose to wait until a debug peripheral is
connected.
SMBus Controller Functional Description
(D31:F3)
Overview
The Intel
SMBus slave interface.
The host controller provides a mechanism for the processor to initiate communications
with SMBus peripherals (slaves). The Intel
in a mode in which it may communicate with I
®
6300ESB ICH provides an SMBus 2.0 compliant Host Controller as well as an
for information regarding bit 0. When the Current Connect
Section 11.2.3.1, “Offset 00h: Control/Status
®
6300ESB ICH is also capable of operating
2
C compatible devices.
for information regarding offset
for information regarding offset
Section 11.2.2.9, “PORTSC-
Intel
®
6300ESB I/O Controller Hub
Register”,
237
DS