NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 546

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

12.2.16 Offset 11H: SLV_CMD—Slave Command Register
Intel
DS
546
Bits
Bits
Default Value:
Default Value:
7:1
7:3
0
2
1
0
®
Table 454. Offset 10h: SLV_STS—Slave Status Register
Table 455. Offset 11H: SLV_CMD—Slave Command Register
6300ESB I/O Controller Hub
Note: This register is in the resume well and is reset by RSMRST#.
Device:
Device:
Offset:
Offset:
HOST_NOTIFY_INTREN
HOST_NOTIFY_WKEN
HOST_NOTIFY_STS
SMBALERT_DIS
Reserved
Reserved
31
10h
00h
Name
31
11h
00h
Name
Reserved.
The Intel
completely received a successful Host Notify Command on
the SMLink pins. Software reads this bit to determine that the
source of the interrupt or SMI# was the reception of the Host
Notify Command. Software clears this bit after reading any
information needed from the Notify address and data
registers by writing a ’1’ to this bit. Note that the Intel
6300ESB ICH will allow the Notify Address and Data registers
to be overwritten once this bit has been cleared. When this
bit is 1, the Intel
address) of any new “Host Notify” commands on the SMLink.
Writing a ’0’ to this bit has no effect.
Reserved.
0 = Allows the generation of the interrupt or SMI#.
1 = Software sets this bit to block the generation of the
Software sets this bit to ’1’ to enable the reception of a Host
Notify command as a wake event. When enabled, this event
is ‘OR’ed in with the other SMBus wake events and is
reflected in the SMB_WAK_STS bit of the General Purpose
Event 0 Status register.
Software sets this bit to ’1’ to enable the generation of
interrupt or SMI# when HOST_NOTIFY_STS is 1. This enable
does not affect the setting of the HOST_NOTIFY_STS bit.
When the interrupt is generated, either PIRQ[B]# or SMI# is
generated, depending on the value of the SMB_SMI_EN bit
(D31, F3, Off40h, B1). If the HOST_NOTIFY_STS bit is set
when this bit is written to a 1, then the interrupt (or SMI#)
will be generated. The interrupt (or SMI#) is logically
generated by ‘AND’ing the STS and INTREN bits.
interrupt or SMI# due to the SMBALERT# source. This bit
is logically inverted and ANDed with the SMBALERT_STS
bit. The resulting signal is distributed to the SMI# and/or
interrupt generation logic. This bit does not affect the
wake logic.
®
6300ESB ICH sets this bit to a ’1’ when it has
®
6300ESB ICH will NACK the first byte (host
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
3
Read/Write Clear
8-bit
3
Read/Write
8-bit
Order Number: 300641-004US
®
Intel
®
6300ESB ICH—12
November 2007
Access
Access
R/WC
R/W
R/W
R/W