NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 179

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.14.2
5.14.2.1 Overview
5.14.2.2 IDE Port Decode
5.14.2.3 IDE Legacy Mode and Native Mode
November 2007
Order Number: 300641-004US
®
Note: The primary and secondary channels are controlled by separate bits, allowing one to be
6300ESB ICH
Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both host
and target throttling of data and transfer rates of up to 33 Mbytes/s.
Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both host
and target throttling of data and transfer rates of up to 66 Mbytes/s.
Ultra ATA/100: DMA protocol that redefines signals on the IDE cable to allow both
host and target throttling of data and transfer rates of up to 100 Mbytes/s.
PIO Transfers
The Intel
modes. The fast timing modes may be enabled only for the IDE data ports. All other
transactions to the IDE registers are run in single transaction mode with compatible
timings.
Up to two IDE devices may be attached per IDE connector (drive 0 and drive 1). The
IDETIM and SIDETIM Registers permit different timing modes to be programmed for
drive 0 and drive 1 of the same connector.
The Ultra ATA/33/66/100 synchronous DMA timing modes may also be applied to each
drive by programming the IDE I/O Configuration register and the Synchronous DMA
Control and Timing registers. When a drive is enabled for synchronous DMA mode
operation, the DMA transfers are executed with the synchronous DMA timings. The PIO
transfers are executed using compatible timings or fast timings when also enabled.
The Command and Control Block registers are accessed differently depending on the
decode mode, which is selected by the Programming Interface configuration register
(Offset 09h).
in native mode and the other in legacy mode simultaneously.
The Intel
mode. In legacy mode, the Command and Control Block registers are accessible at
fixed I/O addresses, may not be accessed through the I/O BARs. These blocks are
decoded when I/O space is enabled through the P-ATA function’s configuration space
and ATA decode is enabled through the PTIM/STIM registers, bit 15. An access to these
addresses results in the assertion of the appropriate chip select (CS1#/CS3#) and the
command strobes (DIOR#, DIOW#).
There are two I/O ranges for each IDE cable: the Command Block, which corresponds
to the CS1P#/CS1S# chip select, and the Control Block, which corresponds to the
CS3P#/CS3S# chip select. The Command Block is an 8 byte range, while the control
block is a 4 byte range.
Table 80
Intel
•
•
Command Block Offset: 01F0h for Primary, 0170h for Secondary
Control Block Offset: 03F4h for Primary, 0374h for Secondary
®
6300ESB ICH hardware definition.
®
®
and
6300ESB ICH IDE controller includes both compatible and fast timing
6300ESB ICH IDE controller supports both legacy mode and PCI native
Table 81
specify the registers and transaction timings as they affect the
Intel
®
6300ESB I/O Controller Hub
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