NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 268

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.20.2.16Input Slot 2: Status Data Port
5.20.2.17Input Slot 3: PCM Record Left Channel
5.20.2.18Input Slot 4: PCM Record Right Channel
5.20.2.19Input Slot 5: Modem Line
5.20.2.20Input Slot 6: Optional Dedicated Microphone Record Data
5.20.2.21Input Slots 7-11: Reserved
5.20.2.22Input Slot 12: I/O Status
Intel
DS
268
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6300ESB I/O Controller Hub
As shown in
sample rate slot request flags for all output slots of the controller. When a slot request
bit is set by the codec, the controller will return data in that slot in the next output
frame. Slot request bits for slots 3 and 4 are always set or cleared in tandem, i.e. both
are set or cleared.
When set, the input slot 1 tag bit only pertains to Status Address Port data from a
previous read. SLOTREQ bits are always valid independent of the slot 1 tag bit.
The status data port receives 16-bit control register read data.
Bit [19:4]: Control Register Read Data
Bit [3:0]: Reserved.
Input slot 3 is the left channel input of the codec. The Intel
16-bit sample resolution. Samples transmitted to the Intel
left/right channel order.
Input slot 4 is the right channel input of the codec. The Intel
16-bit sample resolution. Samples transmitted to the Intel
left/right channel order.
Input slot 5 contains MSB justified modem data. The Intel
bit sample resolution.
Input slot 6 is a third PCM system input channel available for dedicated use by a
microphone. This input channel supplements a true stereo output which enables more
precise echo cancellation algorithm for speakerphone applications. The Intel
ICH supports 16-bit resolution for slot 6 input.
Input frame slots 7-11 are reserved for future use and should be stuffed with zeros by
the codec, per the AC’97 specification.
The status of the GPIOs configured as inputs are to be returned on this slot in every
frame. The data returned on the latest frame is accessible to software by reading the
register at offset 54h/D4h in the codec I/O space. Only the 16 MSBs are used to return
GPI status. In order for GPI events to cause an interrupt, both the 'sticky' and
'interrupt' bits must be set for that particular GPIO pin in regs 50h and 52h. Therefore,
the interrupt will be signalled until it has been cleared by the controller, which may be
much longer than one frame.
Table
139, slot 1 delivers codec control register read address and multiple
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6300ESB ICH supports 16-
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6300ESB ICH must be in
6300ESB ICH must be in
6300ESB ICH supports
6300ESB ICH supports
Order Number: 300641-004US
Intel
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6300ESB ICH—5
November 2007
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6300ESB