NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 739

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NHE6300ESB S L7XJ

Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet

Specifications of NHE6300ESB S L7XJ

Lead Free Status / RoHS Status
Compliant
20—Intel
20.1.2
20.1.3
November 2007
Order Number: 300641-004US
15:0
15:1
Bits
Bits
Default Value:
Default Value:
10
1
9
8
7
6
5
4
Table 662. Offset 02 - 03h: DID—Device ID Register (SATA—D31:F2)
Table 663. Offset 04h - 05h: CMD—Command Register (SATA–D31:F2) (Sheet
Lockable:
Device:
Device:
®
Offset:
Offset:
Postable Memory Write
Parity Error Response
6300ESB ICH
VGA Palette Snoop
Wait Cycle Control
Fast Back-to-Back
Interrupt Disable
Device ID Value
Enable (PMWE)
SERR# Enable
Enable (FBE)
Offset 02 - 03h: DID—Device ID Register (SATA—
D31:F2)
Offset 04h - 05h: CMD—Command Register
(SATA–D31:F2)
1 of 2)
Reserved
31
02-03h
25A3h or 25B0h
No
Name
31
04h-05h
00h
Name
Indicates what device number was assigned by the PCI SIG.
When Device 31 Function 2, Offset AC h, bit 22=0; DID =
25A3h (hard drive)
When Device 31 Function 2, Offset AC h, bit 22=1; DID =
25B0h (RAID)
Reserved.
0 = Enables the SATA host controller to assert INTA# (native
1 = The interrupt will be deasserted and it may not generate
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
0 = Disabled. SATA Controller will not generate PERR# when
a data parity error is detected.
1 = Enabled. SATA Controller will generate PERR# when a
data parity error is detected.
Reserved as ‘0’.
Reserved as ‘0’.
mode), IRQ14/15 (legacy mode), and MSI (when MSI is
enabled).
MSIs.
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
2
Read-Only
16-bit
Core
2
Read-Only, Read/Write
16-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
R/W
RO
RO
RO
RO
RO
739
DS

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