NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 803

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

22—Intel
Table 718. Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Sheet 2 of 2)
November 2007
Order Number: 300641-004US
NOTES:
1. The specification symbols in parentheses correspond to the AT Attachment - 6 with Packet Interface (ATA/
2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) specification for further details on
Sym
t92b
t96a
t96b
t98a
t98b
t93
t94
t95
t97
t99
ATAPI - 6) specification name.
measuring these timing parameters.
®
CRC word valid hold time at sender
(from DMACK# negation until CRC
may become invalid) (see Note 2)
(Tcvh)
STROBE output released-to-driving
to the first transition of critical timing
(Tzfs)
Data Output Released-to-Driving
Until the First Tunisian of Critical
Timing (Tdzfs)
Unlimited Interlock Time (Tui)
Maximum time allowed for output
drivers to release (from asserted or
negated) (Taz)
Minimum time for drivers to assert or
negate (from released) (Tzad)
Ready-to-final-STROBE time (no
STROBE edges shall be sent this long
after negation of DMARDY#) (Trfs)
Maximum time before releasing
IORDY (Tiordyz)
Minimum time before driving IORDY
(see Note 2) (Tziordy)
Time from STROBE edge to negation
of DMARQ or assertion of STOP
(when sender terminates a burst)
(Tss)
6300ESB ICH
Parameter (1)
Min
6.2
70
50
0
0
0
0
Mode 0
(ns)
Max
10
75
20
Min
6.2
48
50
0
0
0
0
Mode 1
(ns)
Max
10
70
20
Min
6.2
31
50
0
0
0
0
Mode 2
(ns)
Intel
Max
10
60
20
®
6300ESB I/O Controller Hub
See
Measurin
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Location
Sender
Sender
Sender
Device
Device
Device
Device
Host
Host
Note 2
g
Figure 5
Figure 5
Figure 5
Figure 5
Figure 5
Figure
5
2
2
2
4
803
DS