NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 380
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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8.6.2.3
Table 264. RTC_REGC—Register C (Flag Register)
8.6.3
Table 265. RTC_REGD—Register D (Flag Register)
Intel
DS
380
Bits
Bits
Default Value:
Default Value:
3:0
5:0
7
6
5
4
7
6
®
RTC Index:
6300ESB I/O Controller Hub
Lockable:
Lockable:
Note: Writes to Register C have no effect.
Device:
Device:
IRQF: Interrupt Request
Offset:
UF: Update-ended Flag
PF: Periodic Interrupt
VRT: Valid RAM and
AF: Alarm Flag
Date Alarm
RTC_REGC—Register C (Flag Register)
RTC_REGD—Register D (Flag Register)
Reserved
Reserved
Time Bit
31
0Ch
00U00000 (U:
Undefined)
No
Name
31
0Dh
10UUUUUU (U:
Undefined)
No
Name
Flag
Flag
IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE). This also causes
the CH_IRQ_B signal to be asserted. This bit is cleared upon
RSMRST# or a read of Register C.
This bit is cleared upon RSMRST# or a read of Register C.
0 = When no taps are specified through the RS bits in
1 = Periodic interrupt Flag will be 1 whenever the tap
0 = This bit is cleared upon RTCRST# or a read of Register C.
1 = Alarm Flag will be set after all Alarm values match the
0 = The bit is cleared upon RSMRST# or a read of Register C.
1 = Set immediately following an update cycle for each
Reserved. Will always report 0.
0 = This bit should always be written as a 0 for write cycle,
1 = This bit is hard-wired to 1 in the RTC power well.
Reserved. This bit always returns a 0 and should be set to 0
for write cycles.
These bits store the date of month alarm value. When set to
000000b, then a “does not care” state is assumed. The host
must configure the date alarm for these bits to do anything,
yet they may be written at any time. When the date alarm is
not enabled, these bits will return zeros to mimic the
functionality of the Motorola 146818B. These bits are not
affected by RESET.
Register A, this flag will not be set.
specified by the RS bits of register A is 1.
current time.
second.
however it will return a 1 for read cycles.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read-Only
8-bit
RTC
0
Read/Write
8-bit
RTC
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
Access
R/W
R/W
RO
RO
RO
RO
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