NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 456

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

9—Intel
9.2.1
Bits
Default Value:
November 2007
Order Number: 300641-004US
7:4
2:1
3
0
Table 348. BMIC[P,S]—Bus Master IDE Command Register
®
Device:
Offset:
6300ESB ICH
Start/Stop Bus Master
Read / Write Control
BMIC[P,S]—Bus Master IDE Command
Register
Reserved
Reserved
(START)
Name
(RWC)
31
Primary: 00h
Secondary: 08h
00h
Reserved. Returns ‘0’.
This bit sets the direction of the bus master transfer: This bit
must NOT be changed when the bus master function is active.
0 = Memory reads
1 = Memory writes
Reserved. Returns ’0’.
0 = All state information is lost when this bit is cleared.
1 = Enables bus master operation of the controller. Bus
NOTE: This bit is intended to be cleared by software after the
Master mode operation cannot be stopped and then
resumed. When this bit is reset while bus master
operation is still active (i.e., the Bus Master IDE Active bit
of the Bus Master IDE Status register for that IDE
channel is set) and the drive has not yet finished its data
transfer (the Interrupt bit in the Bus Master IDE Status
register for that IDE channel is not set), the bus master
command is said to be aborted and data transferred from
the drive may be discarded instead of being written to
system memory.
master operation begins when this bit is detected
changing from a zero to a one. The controller will transfer
data between the IDE device and memory only when this
bit is set. Master operation may be halted by writing a '0'
to this bit.
data transfer is completed, as indicated by either the
Bus Master IDE Active bit being cleared or the
Interrupt bit of the Bus Master IDE Status register for
that IDE channel being set, or both. Hardware does
not clear this bit automatically.
Description
Attribute:
Function:
Size:
1
Read/Write
8-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
456
DS