NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 517

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11—Intel
Table 418. Offset CAPLENGTH + 18 - 1Bh: ASYNCLISTADDR—Current
11.2.2.8 Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure
Table 419. Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure Flag Register
11.2.2.9 PORTSC- Port N Status and Control
November 2007
Order Number: 300641-004US
31:5
31:1
Bits
Bits
Default Value:
Default Value:
4:0
0
Note: A host controller must implement one or more port registers. Software uses the N_Port
Device:
Device:
®
Offset:
Offset:
Link Pointer Low (LPL)
6300ESB ICH
Configure Flag (CF)
Asynchronous List Address
Flag Register
information from the Structural Parameters Register to determine how many ports
need to be serviced. All ports have the structure defined below. Software must not
write to unreported Port Status and Control Registers.
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset. The initial
conditions of a port are:
Reserved
Reserved
1. No device connected.
2. Port disabled. When a device is attached, the port state transitions to the attached
3. When a port is being used as the Debug Port, the port may report device connected
29
CAPLENGTH + 18-1Bh
00000000h
Name
29
CAPLENGTH + 40-43h
00000000h
Name
state and system software will process this as with any status change notification.
Refer to Section 4 of the EHCI Specification for operational requirements for how
change events interact with port suspend mode
and enabled when the Configured Flag is a ’0’.
These bits correspond to memory address signals [31:5],
respectively. This field may only reference a Queue Head
(QH).
Reserved. These bits are reserved and their value has no
effect on operation.
Reserved. Read from this field will always return 0.
Default 0b. Host software sets this bit as the last action in its
process of configuring the Host Controller. This bit controls
the default port-routing control logic. Bit values and side
effects are listed below. See Section 4 of the EHCI
Specification for operational details.
0 = Port routing control logic default–routes each port to the
1 = Port routing control logic default–routes all ports to this
classic host controllers.
host controller.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
7
Read/Write
32-bit
7
Read/Write
32-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
RW
RW
517
DS