NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 335

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.1.29
Table 209. Offset E3h: FWH_DEC_EN1—FWH Decode Enable 1 Register (LPC I/F—
November 2007
Order Number: 300641-004US
Bits
Default Value:
7
6
5
4
3
Lockable:
®
Note: This register determines which memory ranges will be decoded on the PCI bus and
Device:
Offset:
6300ESB ICH
FWH_D8_EN
FWH_F8_EN
FWH_F0_EN
FWH_E8_EN
FWH_E0_EN
Offset E3h: FWH_DEC_EN1—FWH Decode Enable 1
Register (LPC I/F—D31:F0)
forwarded to the FWH. The Intel
unless POS_DEC_EN is set to 1.
D31:F0) (Sheet 1 of 2)
31
E3h
FFh
No
Name
Enables decoding two 512 Kbyte FWH memory ranges, and
one 128 Kbyte memory range.
0 = Disable
1 = Enable the following ranges for the FWH
Enables decoding two 512 Kbyte FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH:
Enables decoding two 512 Kbyte FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH:
Enables decoding two 512 Kbyte FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH:
Enables decoding two 512 Kbyte FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FFF80000h - FFFFFFFFh
FFB80000h - FFBFFFFFh
000E0000h - 000FFFFFh
FFF00000h - FFF7FFFFh
FFB00000h - FFB7FFFFh
FFE80000h - FFEFFFFh
FFA80000h - FFAFFFFFh
FFE00000h - FFE7FFFFh
FFA00000h - FFA7FFFFh
FFD80000h - FFDFFFFFh
FF980000h - FF9FFFFFh
®
6300ESB ICH will subtractively decode cycles on PCI
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
8-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
R/W
R/W
RO
335
DS