MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 10

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

6.2.2.5
6.2.2.5.1
6.2.2.5.2
6.2.2.5.3
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.2
7.3
7.4
7.5
7.5.1
7.5.2
7.5.3
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.3
8.4
Freescale Semiconductor
Paragraph
Number
Reset Operation ............................................................................................................... 7-1
Reset Actions Summary .................................................................................................. 7-3
Data Coherency During Reset ........................................................................................ 7-4
Reset Status Register (RSR) ........................................................................................... 7-5
Reset Configuration ........................................................................................................ 7-7
System Clock Sources .................................................................................................... 8-3
System PLL ..................................................................................................................... 8-3
System Clock During PLL Loss of Lock ........................................................................ 8-6
Low-Power Divider ........................................................................................................ 8-6
Power-On Reset .......................................................................................................... 7-1
Hard Reset ................................................................................................................... 7-2
Soft Reset .................................................................................................................... 7-2
Loss of PLL Lock ....................................................................................................... 7-2
On-Chip Clock Switch ................................................................................................ 7-3
Software Watchdog Reset ........................................................................................... 7-3
Checkstop Reset .......................................................................................................... 7-3
Debug Port Hard Reset ............................................................................................... 7-3
Debug Port Soft Reset ................................................................................................. 7-3
JTAG Reset ................................................................................................................. 7-3
ILBC Illegal Bit Change ............................................................................................. 7-3
Hard Reset Configuration ........................................................................................... 7-7
Hard Reset Configuration Word (RCW) .................................................................. 7-11
Soft Reset Configuration .......................................................................................... 7-13
Frequency Multiplication ............................................................................................ 8-4
Skew Elimination ........................................................................................................ 8-4
Pre-Divider .................................................................................................................. 8-4
PLL Block Diagram .................................................................................................... 8-4
PLL Pins ..................................................................................................................... 8-5
General-Purpose I/O Registers ............................................................................. 6-46
SGPIO Data Register 1 (SGPIODT1) ............................................................. 6-46
SGPIO Data Register 2 (SGPIODT2) ............................................................. 6-47
SGPIO Control Register (SGPIOCR) .............................................................. 6-48
MPC561/MPC563 Reference Manual, Rev. 1.2
Clocks and Power Control
Contents
Chapter 7
Chapter 8
Reset
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Number
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