MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 720

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

CAN 2.0B Controller Module
16-26
12:15
Bits
10
11
6
7
8
9
SELFWAKE Self wake enable. This bit allows the TouCAN to wake up when bus activity is detected after
SOFTRST
STOPACK
FRZACK
Name
SUPV
APS
—
Soft reset. When this bit is asserted, the TouCAN resets its internal state machines
(sequencer, error counters, error flags, and timer) and the host interface registers
(CANMCR, CANICR, CANTCR, IMASK, and IFLAG).
The configuration registers that control the interface with the CAN bus are not changed
(CANCTRL[0:2] and PRESDIV). Message buffers and receive message masks are also not
changed. This allows SOFTRST to be used as a debug feature while the system is running.
Setting SOFTRST also clears the STOP bit in CANMCR.
After setting SOFTRST, allow one complete bus cycle to elapse for the internal TouCAN
circuitry to completely reset before executing another access to CANMCR.
The TouCAN clears this bit once the internal reset cycle is completed.
0 Soft reset cycle completed
1 Soft reset cycle initiated
TouCAN disable. When the TouCAN enters debug mode, it sets the FRZACK bit. This bit
should be polled to determine if the TouCAN has entered debug mode. When debug mode
is exited, this bit is negated once the TouCAN prescaler is enabled. This is a read-only bit.
0 The TouCAN has exited debug mode and the prescaler is enabled
1 The TouCAN has entered debug mode, and the prescaler is disabled
Supervisor/user data space. The SUPV bit places the TouCAN registers in either supervisor
or user data space.
0 Registers with access controlled by the SUPV bit are accessible in either user or
1 Registers with access controlled by the SUPV bit are restricted to supervisor mode
the STOP bit is set. If this bit is set when the TouCAN enters low-power stop mode, the
TouCAN will monitor the bus for a recessive to dominant transition. If a recessive to dominant
transition is detected, the TouCAN immediately clears the STOP bit and restarts its clocks.
If a write to CANMCR with SELFWAKE set occurs at the same time a recessive-to-dominant
edge appears on the CAN bus, the bit will not be set, and the module clocks will not stop.
The user should verify that this bit has been set by reading CANMCR. Refer to
Section 16.5.2, “Low-Power Stop
low-power stop mode.
0 Self wake disabled
1 Self wake enabled
Auto power save. The APS bit allows the TouCAN to automatically shut off its clocks to save
power when it has no process to execute, and to automatically restart these clocks when it
has a task to execute without any CPU intervention.
0 Auto power save mode disabled; clocks run normally
1 Auto power save mode enabled; clocks stop and restart as needed
Stop acknowledge. When the TouCAN is placed in low-power stop mode and shuts down its
clocks, it sets the STOPACK bit. This bit should be polled to determine if the TouCAN has
entered low-power stop mode. When the TouCAN exits low-power stop mode, the STOPACK
bit is cleared once the TouCAN’s clocks are running.
0 The TouCAN is not in low-power stop mode and its clocks are running
1 The TouCAN has entered low-power stop mode and its clocks are stopped
Reserved. These bits are used for the IARB (interrupt arbitration ID) field in TouCAN
implementations that use hardware interrupt arbitration.
Table 16-11. CANMCR Bit Descriptions (continued)
supervisor privilege mode
MPC561/MPC563 Reference Manual, Rev. 1.2
Mode” for more information on entry into and exit from
Description
Freescale Semiconductor