MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 341

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Chapter 9
External Bus Interface
The MPC561/MPC563 external bus is a synchronous, burstable bus. Signals driven on this bus must
adhere to the setup and hold time relative to the bus clock’s rising edge. The bus has the ability to support
multiple masters. The MPC561/MPC563 external bus interface architecture supports byte, half-word, and
word operands allowing access to 8-, 16-, and 32-bit data ports through the use of synchronous cycles
controlled by the size outputs (TSIZ0, TSIZ1). For accesses to 16- and 8-bit ports, the slave must be
controlled by the memory controller. For more information, refer to
Characteristics.”
9.1
The external bus interface features are listed below:
9.2
The bus transfers information between the MPC561/MPC563 and external memory of a peripheral device.
External devices can accept or provide 8, 16, and 32 data bits in parallel and must follow the handshake
protocol described in this section. The maximum number of bits accepted or provided during a bus transfer
is defined as the port width.
The MPC561/MPC563 has non-multiplexed address and data buses. Control signals indicate the
beginning and type of the cycle, as well as the address space and size of the transfer. The selected device
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
32-bit address bus with transfer size indication (only 24 available on pins)
32-bit data bus
Bus arbitration logic on-chip with external master support
Chip-select and wait state generation to support peripheral or static memory devices through the
memory controller
Supports various memory (SRAM, EEPROM) types: synchronous and asynchronous, burstable
and non-burstable
Supports non-wrap bursts with up to four data beats
Flash ROM programming support
Implements the PowerPC ISAarchitecture
Easy to interface to slave devices
Bus is synchronous (all signals are referenced to rising edge of bus clock)
Bus can operate at the same frequency as the internal RCPU core of MPC561/MPC563 or half the
frequency.
Features
Bus Transfer Signals
MPC561/MPC563 Reference Manual, Rev. 1.2
Appendix F, “Electrical
9-1