MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1202

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

TPU3 ROM Functions
D-50
ADDRESS OFFSETS
ADDRESS OFFSETS
0x30XXWA
0x30XXWC
0x30XXWE
0x30XXWA
0x30XXWC
0x30XXWE
0x30XXW0
0x30XXW2
0x30XXW4
0x30XXW6
0x30XXW8
0x30XXW0
0x30XXW2
0x30XXW4
0x30XXW6
0x30XXW8
= Written By RCPU
= Written By TPU
0
0
START_LINK_
CHANNEL
Figure D-29. SPWM Parameters (continued)
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
LASTRISE
LASTRISE
2
2
REF_ADDR1
PARAMETER RAM (MODE 1)
PARAMETER RAM (MODE 2)
3
3
LINK_CHANNEL_
4
4
= Written by RCPU and TPU
= Unused Parameters
COUNT
5
5
6
6
REF_VALUE
HIGH_TIME
HIGH_TIME
NEXTRISE
NEXTRISE
PERIOD
DELAY
DELAY
7
7
BITS
BITS
8
8
CHANNEL_CONTROL
CHANNEL_CONTROL
9
9
10 11 12 13 14 15
10 11 12 13 14 15
REF_ADDR2
REF_ADDR1
W = Channel Number
For address offsets: XX=41 for
TPU_A, 45 for TPU_B
YY=40 for TPU_A,
See
PRAM Address Offset Map.
44 for TPU_B
Table 19-24
Freescale Semiconductor
for the
Param 0
Param 1
Param 2
Param 3
Param 4
Param 5
Param 6
Param 7
Param 0
Param 1
Param 2
Param 3
Param 4
Param 5
Param 6
Param 7