MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 688

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Queued Serial Multi-Channel Module
15.8.8
The block diagram of the enhancements to the SCI receiver is shown below in
15.8.9
Additional QSCI1 features include:
15-70
Receiver Baud Rate
Clock
SCI1 Non-Queue Operation
•
•
Available on a single SCI channel (SCI1) implemented by the queue receiver enable (QRE) bit set
by software. When the queue is enabled, software should ignore the RDRF bit.
When the queue is disabled (QRE = 0), the SCI functions in single buffer receive mode (as
originally designed) and RDRF and OR function as previously defined. Locations SCRQ[0:15] can
QSCI1 Receiver Block Diagram
QSCI1 Additional Receive Operation Features
RxD
Queue Control
Figure 15-38. Queue Receiver Block Enhancements
MPC561/MPC563 Reference Manual, Rev. 1.2
H (8) 7 6 5 4 3 2 1 0 L
SCxDR Rx BUFFER
10 (11) - Bit
Rx Shift Register
Queue Status
4-bits
Queue Control
Logic
SCI Interrupt Request
SCRQ0
SCRQ1
SCRQ15
Figure
Freescale Semiconductor
15-38.
Data Bus