MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 830

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Peripheral Pin Multiplexing (PPM) Module
18.4.12
SCALE_TCLK_REG is used to set the rate of the PPM_TCLK that provides the timing for data transfer
into and out of the PPM module. The PPM_TCLK frequency is derived from the system clock, F
PPM_TCLK is software programmable using the following formula:
The range of PPM_TCLK frequencies available is:
18-24
SRESET
Bits
9:15
0:8
Field
Addr
F
PPM_TCLK
Scale Transmit Clock Register (SCALE_TCLK_REG)
MSB
SHORT_CH_REG
0
Data transmitted
Data transmitted
Register Name
TX_DATA[0:15]
SCT[6:0]
Name
—
Figure 18-27. Scale Transmit Clock Register (SCALE_TCLK_REG)
1
= F
Table 18-11. Examples of the SHORT_CH Bits (continued)
SYSCLK
2
Table 18-13. SCALE_TCLK_REG Bit Descriptions
Reserved
Determines the frequency of PPM_TCLK.
Writing to SCT[6:0] while the PPM is enabled will cause an irregular PPM cycle to
occur.
• SCT[6:0] = 0 F
• SCT[6:0] = 1 to 127 F
RESERVED
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 18-12. SCALE_TCLK Frequencies
F
/ (2 * SCT[6:0])
SYSCLK
Minimum
4
Contents
Register
0x00FF
0x303C
0x3034
0x1234
/256
5
SYSCLK
0000_0000_0000_0000
Example 3
6
SYSCLK
/256
0x30 5C2A
0b 0011 0000 0011 0100
SHORT_CH[7:0] = 1, therefore bits (TX_DATA[1, 3, 5,
7, 9, 11, 13, 15] are enabled for re-transmission.
0b 0001 0010 0011 0100
Underlines show bits to be re-transmitted
0b 0011 0000 0011 1100
7
/ (2 * SCT[6:0])
8
Maximum
F
Description
SYSCLK
9
/2
10
Comments
11
SCT[6:0]
12
Freescale Semiconductor
13
14
SYSCLK
LSB
15
.