MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 630

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Queued Serial Multi-Channel Module
15.5.2
PQSPAR determines which of the QSPI pins, with the exception of the SCK pin, are used by the QSPI
submodule, and which pins are available for general-purpose I/O. Pins may be assigned on a pin-by-pin
basis. If the QSPI is disabled, the SCK pin is automatically assigned its general-purpose I/O function
(QGPIO6).
QSPI pins designated by PQSPAR as general-purpose I/O pins are controlled only by PQSDDR and
PQSPDR; the QSPI has no effect on these pins. PQSPAR does not affect the operation of the SCI
submodule.
Table 15-9
15-12
SRESET
Field
Addr
summarizes the QSMCM pin functions.
PORTQS Pin Assignment Register (PQSPAR)
MSB
0
1
0000
—
2
PORTQS Function
3
QGPIO6
QGPIO5
QGPIO4
QGPIO3
QGPIO2
QGPIO1
QGPIO0
Figure 15-7. PORTQS — Port QS Data Register
QGPO2
QGPO1
QGPI2
QGPI1
QDR
XD2
MPC561/MPC563 Reference Manual, Rev. 1.2
4
0
Table 15-9. QSMCM Pin Functions
QDT
XD2
1
5
QDR
XD1
QSMCM Function
0
6
RXD2
TXD2
RXD1
TXD1
PCS3
PCS2
PCS1
PCS0
MOSI
MISO
QDT
XD1
SCK
1
7
0x30 5014
0
0
8
QDP
CS3
0
9
Alternate Function
C_CNRX0
QDP
C_CNTX0
CS2
10
0
—
—
—
—
—
—
—
—
—
QDP
CS1
11
0
QDPC
S0
12
0
Freescale Semiconductor
QDS
CK
13
0
QDM
OSI
14
0
QDM
ISO
LSB
15
0