MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 828

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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Peripheral Pin Multiplexing (PPM) Module
18.4.11
SHORT_CH_REG allows the shorting of transmit channels from the PPM using the bit field SHORT[7:0].
The PPM normally transmits data by right-shifting TX_DATA at the rate of one bit per PPM_TCLK cycle,
TX_DATA15 first. Shorts can be enabled for transmit data bits TX_DATA[1, 3, 5, 7, 9, 11, 13, and 15].
Where a short is enabled for any of these transmit data bits, that bit will be transmitted for two PPM_TCLK
cycles, during its own bit time and the bit time of the following transmit data bit.
18-22
SH_TPU1
1
1
1
1
0
Short Channels Register (SHORT_CH_REG)
If SHORT_CHx = 1, transmit TX_DATAx during TX_DATAx bit time and
repeat TX_DATAx during TX_DATA[x-1] bit time.
MPC561/MPC563
A_TPUCH1
Output
Output
Input
Input
TPU_B
TPU_A
X
Table 18-9. SHORT_REG[SH_TPU] Bit Settings
Figure 18-25. Short Between TPU Channels
MPC561/MPC563 Reference Manual, Rev. 1.2
B_TPUCH1
A_CH
B_CH
Output
Output
Input
Input
X
Data on pad A_TPUCH1 will be the input to A_TPUCH1 and
B_TPUCH1
Output data on B_TPUCH1 will be the input to A_TPUCH1
Output on A_TPUCH1 will be the input data to B_TPUCH1
No Short
No Short
EXAMPLE
Pad
Pad
Effect on TPU3 Modules
B_TPUCH
A_TPUCH
Freescale Semiconductor

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