MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 167

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

3.9.3
After an alignment exception, the DAR, SPR 19, is set to the effective address of a load or store element.
3.9.4
Refer to
3.9.5
Refer to
3.9.6
The machine status save/restore register 0 (SRR0), SPR 26, identifies where instruction execution should
resume when an rfi instruction is executed following an exception. It also holds the effective address of
the instruction that follows the system call (sc) instruction.
When an exception occurs, SRR0 is set to point to an instruction such that all prior instructions have
completed execution and no subsequent instruction has begun execution. The instruction addressed by
SRR0 may not have completed execution, depending on the exception type. SRR0 addresses either the
instruction causing the exception or the instruction immediately following. The instruction addressed can
be determined from the exception type and status bits.
3.9.7
The machine status save/restore register 1 (SRR1), SPR 27, saves the machine status on exceptions and
restores the machine status when an rfi instruction is executed.
Freescale Semiconductor
Reset
Reset
Field
Addr
Field
Addr
Section 6.1.7, “Time Base
Section 6.1.6, “Decrementer
MSB
Data Address Register (DAR)
Time Base Facility (TB) — OEA
Decrementer Register (DEC)
Machine Status Save/Restore Register 0 (SRR0)
Machine Status Save/Restore Register 1 (SRR1)
MSB
0
0
1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
2
3
Figure 3-14. Machine Status Save/Restore Register 0 (SRR0)
4
5
6
7
Figure 3-13. Data Address Register (DAR)
MPC561/MPC563 Reference Manual, Rev. 1.2
8
(TB),” for information.
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(DEC),” for information.
Data Address
Unchanged
Undefined
SPR 26
SPR 19
SRR0
Central Processing Unit
LSB
31
LSB
31
3-23