MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 860

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Dual-Port TPU3 RAM (DPTRAM)
20.3.5
The MISCNT contains the address of the current MISC memory access. This register is read-only. Note
that the naming of the A[31:0] bits represents little-endian bit encoding.
Exiting TPU3 emulation mode or clearing the MISEN bit in the DPTMCR results in the reset of this
register.
20.4
The DPTRAM module has several modes of operation. The following sections describe DPTRAM
operation in each of these modes.
20.4.1
In normal operation, read or write data accesses of 8-, 16-, or 32-bits are supported. Also, in normal
operation, neither TPU3 accesses the array, nor do they have any effect on the operation of the DPTRAM
module.
20.4.2
The DPTRAM array uses a separate power supply IRAMSTBY to provide power to the DPTRAM array
during a power-down phase.
In order to guarantee valid DPTRAM data during power-down, external low voltage inhibit circuitry
(external to the MPC561/MPC563) must be designed to force the RESET pin of the MPC561/MPC563
into the active state before V
to the DPTRAM during power-down.
20-6
SRESET
SRESET
Field
Addr
Field
Addr
DPTRAM Operation
MISC Counter (MISCNT)
Normal Operation
Standby Operation
MSB
MSB
D15
0
0
—
D14
1
1
Figure 20-6. Multiple Input Signature Register Low (MISRL)
2
D13
2
DD
A12
3
D12
3
drops below its normal limit. This is necessary to inhibit spurious writes
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 20-7. MISC Counter (MISCNT)
A11
D11
4
4
A10
D10
5
5
A9
0000_0000_0000_0000
6
D9
Last Memory Address
6
A8
0x30 0008
7
0x30 000A
D8
7
A7
D7
8
8
A6
D6
9
9
A5
10
D5
10
A4
D4
11
11
A3
D3
12
12
Freescale Semiconductor
D2
A2
13
13
D1
A1
14
14
LSB
D0
LSB
15
A0
15