MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 812

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Peripheral Pin Multiplexing (PPM) Module
SCALE_TCLK_REG. The transmit signals, PPM_TX, will stay high as long as PPM_TSYNC is high
(equal to “1” in
Complete transmit and receive cycles are based on the PPM_TSYNC clock. A cycle begins on the rising
edge of PPM_TSYNC, which goes high for one PPM_TCLK cycle. The transmit signals, PPM_TX[0:1],
will stay high as long as PPM_TSYNC is high (equal to “1” in
the falling edge of PPM_TSYNC. In receive mode, valid data starts to shift into RX_SHIFTER on the
falling edge of PPM_TSYNC. PPM_TSYNC stays low until the contents of TX_DATA have been shifted
out and/or 16 bits have been shifted into RX_SHIFTER. One data bit is transferred every PPM_TCLK
cycle.
18-6
PPM_TSYNC
PPM_TCLK1
PPM_TCLK2
PPM_TCLK2
PPM_RX
PPM_TX
SYSCLK
(see
PPM_TCLK1 — TCLK in TDM Mode
PPM_TCLK2 — TCLK in SPI Mode
PPM_CLK2 — TCLK in SPI Mode, with inverted SPI clock polarity enabled
f
TCLK
Section 18.4.12, “ Scale Transmit Clock Register (SCALE_TCLK_REG)
= (f
Figure
Shading of PPM_RX signifies value is unknown
SYSCLK
18-5).
/2*N) where N is the value in SCALE_TCLK_REG
Figure 18-5. PPM Clocks and Serial Data Signals
MPC561/MPC563 Reference Manual, Rev. 1.2
“1”
CHANNEL0
CHANNEL0
Figure
CHANNEL1
CHANNEL1
18-6). Data bits start to transmit on
CHANNEL2
CHANNEL2
Freescale Semiconductor