MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 491

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

During the freeze mode, the queue status field is not modified. The queue status field retains the status it
held prior to freezing. As a result, the queue status can show queue 1 active, queue 2 idle, even though
neither queue is being executed during freeze.
13.3.9
The conversion command word (CCW) table is a RAM, 64 words long on 16-bit address boundaries where
10-bits of each entry are implemented. A CCW can be programmed by the software to request a conversion
of one analog input channel. The CCW table is written by software and is not modified by the QADC64E.
Each CCW requests the conversion of an analog channel to a digital result. The CCW specifies the analog
channel number, the input sample time, and whether the queue is to pause after the current CCW. The ten
implemented bits of the CCW word are read/write data, where they may be written when the software
initializes the QADC64E. The remaining 6-bits are unimplemented so these read as zeros, and write
Freescale Semiconductor
SRESET
10:15
Bits
0:1
2:7
8:9
Field
Addr
Conversion Command Word Table
MSB
CWPQ1
CWPQ2
0
Name
00
—
—
—
1
Reserved
Command Word Pointer for Q1 . CWPQ1 allows the software to know what CCW was last
completed for queue 1. This field is a software read-only field, and write operations have
no effect. CWPQ1 allows software to read the last executed CCW in queue 1, regardless
of which queue is active. The CWPQ1 field is a CCW word pointer with a valid range of 0
to 63.
In contrast to CWP, CPWQ1 is updated when the conversion result is written. When the
QADC64E finishes a conversion in queue 1, both the result register is written and the
CWPQ1 are updated.
Finally, when queue 1 operation is terminated after a CCW is read that is defined as BQ2,
CWP points to BQ2 while CWPQ1 points to the last CCW queue 1.
During the stop mode, the CWPQ1 is reset to 63, since the control registers and the analog
logic are reset. When the freeze mode is entered, the CWPQ1 is unchanged; it points to
the last executed CCW in queue 1.
Reserved
Command Word Pointer for Q2. CWPQ2 allows the software to know what CCW was last
completed for queue 2. This field is a software read-only field, and write operations have
no effect. CWPQ2 allows software to read the last executed CCW in queue 2, regardless
which queue is active. The CWPQ2 field is a CCW word pointer with a valid range of 0 to
63.
In contrast to CWP, CPWQ2 is updated when the conversion result is written. When the
QADC64E finishes a conversion in queue 2, both the result register is written and the
CWPQ2 are updated.
During the stop mode, the CWPQ2 is reset to 63, since the control registers and the analog
logic are reset. When the freeze mode is entered, the CWP is unchanged; it points to the
last executed CCW in queue 2.
2
3
Figure 13-14. Status Register 1 (QASR1)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 13-17. QASR1 Bit Descriptions
11_1111
CWPQ1
0x30 4812 (QASR1_A); 0x30 4C12 (QASR1_B)
4
5
6
7
Description
8
00
—
9
10
11
QADC64E Legacy Mode Operation
12
11_1111
CWPQ2
13
14
LSB
15
13-27