MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 209

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

4.1.2
4.1.3
The following are instruction code decompression unit key features of the MPC562/MPC564. See
Appendix A, “MPC562/MPC564 Compression
Freescale Semiconductor
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Implements a parked master on the U-bus, resulting in zero clock delays for RCPU fetch accesses
to the U-bus
Fully utilizes the U-bus pipeline for fetch accesses
Avoids undesirable delays through a tight interface with the L2U module (fully utilizing U-bus
bandwidth and back-to-back accesses)
Supports program trace and show cycles
Supports a special attribute for debug port fetch accesses.
There are four regions in which the base address and size can be programmed.
Available region sizes include 2 Kbytes, 8 Kbytes, 16 Kbytes, 32 Kbytes, 64 Kbytes, 128 Kbytes,
256 Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, 16 Mbytes....4 Gbytes.
Overlap between regions is allowed.
Each of the four regions supports the following attributes:
— User/supervisor
— Guard attribute (causes an interrupt in case of speculative fetch attempt)
— Compressed/non-compressed (MPC562/MPC564 only)
— Regions are enabled or disabled in software.
Global region entry declares the default access attributes for all memory areas not covered by the
four regions:
The RCPU gets the instruction storage protection exception generated upon
— An access violation of protection attributes
— A fetch from a guarded region.
The RCPU MSR[IR] bit controls IMPU protection.
Programming is performed by using the RCPU mtspr/mfspr instructions to/from implementation
specific special-purpose registers.
The IMPU supplies relocation addresses of all the exceptions within the internal memory space.
The IMPU implements external interrupt vector splitting to reduce the external interrupt latency.
There is a special reset exception vector for decompression on mode (MPC562/MPC564 only).
Instruction code on-line decompression based on “instruction classes” algorithm.
No need for address translation between compressed and non-compressed address spaces — ICDU
provides “next instruction address” to the RCPU
In most cases, instruction decompression takes one clock
Code decompression is pipelined:
IMPU Key Features
ICDU Key Features
MPC561/MPC563 Reference Manual, Rev. 1.2
Features” for more information.
Burst Buffer Controller 2 Module
4-3