MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 200

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
When a floating-point exception is taken, instruction execution resumes at offset 0x0E00 from the base
address indicated by MSR[IP].
3.15.4.13 Implementation-Dependent Software Emulation Exception (0x1000)
An implementation-dependent software emulation exception occurs in the following instances:
Table 3-34
3-56
1
•
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Machine State Register (MSR)
When executing any non-implemented instruction. This includes all illegal and unimplemented
optional instructions and all floating-point instructions.
When executing a mtspr or mfspr instruction that specifies an un-implemented
internal-to-the-processor SPR, regardless of the value of bit 0 of the SPR.
When executing a mtspr or mfspr that specifies an un-implemented external-to-the-processor
register and SPR0 = 0 or MSR[PR] = 0 (no program interrupt condition).
shows the register settings set when a software emulation exception occurs.
Register Name
Register Name
Table 3-33. Register Settings following Floating-Point Assist Exceptions
Table 3-34. Register Settings following a Software Emulation Exception
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
10:15
Other
Other
10:15
Other
Bits
Bits
ME
1:4
1:4
LE
All
IP
Cleared to 0
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Set to the effective address of the instruction that caused the
interrupt
Cleared to 0
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI].
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
No change
Cleared to 0
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
Description
Description
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