MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1125

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
0x30 4812
0x30 4814 –
0x30 49FE
0x30 4A00 –
0x30 4A7E
0x30 4A80 –
0x30 4AFE
0x30 4B00 –
0x30 4B7E
0x30 4B80 –
0x30 4BFE
0x30 4C00
0x30 4C02
0x30 4C04
0x30 4C06
0x30 4C08
0x30 4C0A
0x30 4C0C
0x30 4C0E
0x30 4C10
0x30 4C12
0x30 4C14 –
0x30 4DFE
0x30 4E00 –
0x30 4E7E
0x30 4E80 –
0x30 4EFE
Address
Table B-10. QADC64E A and B (Queued Analog-to-Digital Converter) (continued)
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
—
—
S
T
S
1
1
QADC64MCR_B QADC64 Module Configuration Register
QADC64TEST_
QADC64INT_B
PORTQA_B/
PORTQB_B
DDRQA_B/
DDRQB_B
QASR1_A
RJURR_A
QACR0_B
QACR1_B
QACR2_B
QASR0_B
QASR1_B
RJURR_B
LJURR_A
LJSRR_A
Symbol
CCW_A
CCW_B
MPC561/MPC563 Reference Manual, Rev. 1.2
—
—
B
QADC64 Status Register 1.
See
descriptions.
Reserved
Conversion Command Word Table.
See
descriptions.
Result Word Table
Right-Justified, Unsigned Result Register.
See
bit descriptions.
Result Word Table
Left-Justified, Signed Result Register.
See
bit descriptions.
Result Word Table
Left-Justified, Unsigned Result Register.
See
bit descriptions.
QADC64 Test Register
Interrupt Register
Port A and Port B Data
Port A Data and Port B Direction Register
QADC64 Control Register 0
QADC64 Control Register 1
QADC64 Control Register 2
QADC64 Status Register 0
QADC64 Status Register 1
Reserved
Conversion Command Word Table
Result Word Table.
Right-Justified, Unsigned Result Register.
Table 13-17
Table 13-18
Section 13.3.10
Section 13.3.10
Section 13.3.10
QADC_B
and
and
Register
and
and
and
Table 14-18
Table 14-19
Section 14.3.10
Section 14.3.10
Section 14.3.10
for bit
for bit
for
for
for
Size
16
16
—
16
16
16
16
16
16
16
16
16
16
16
16
16
—
16
16
Internal Memory Map
Reset
—
—
—
S
U
X
X
X
S
S
U
S
S
S
S
S
S
U
X
B-15