MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 846

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Time Processor Unit 3
19.4.7
The host sequence field selects the mode of operation for the time function selected on a given channel.
The meaning of the host sequence bits depends on the time function specified. See
ROM
19-16
SRESET
SRESET
SRESET
SRESET
Field
Addr
Field
Addr
Functions,” for definitions of the host service request bits for the predefined TPU ROM functions.
Field
Field
Addr
Addr
CH[15:0]
Name
MSB
MSB
0
Host Sequence Registers (HSQRn)
MSB
MSB
0
0
0
1
1
CH 7
1
1
Encoded time function for each channel. Encoded four-bit fields in the channel function select
registers specify one of 16 time functions to be executed on the corresponding channel.
CH 3
CH 15
CH 11
Figure 19-10. CFSR0 — Channel Function Select Register 0
Figure 19-11. CFSR1 — Channel Function Select Register 1
Figure 19-12. CFSR2 — Channel Function Select Register 2
Figure 19-13. CFSR3 — Channel Function Select Register 3
2
2
2
2
3
3
3
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 19-12. CFSRn Bit Descriptions
4
4
4
4
0x30 400C (TPU_A), 0x30 440C (TPU_B)
0x30 400E (TPU_A), 0x30 440E (TPU_B)
0x30 4010 (TPU_A), 0x30 4410 (TPU_B)
0x30 4012 (TPU_A), 0x30 4412 (TPU_B)
5
5
5
5
CH 14
CH 10
CH 6
CH 2
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
6
6
6
6
7
7
7
7
Description
8
8
8
8
9
9
9
9
CH 13
CH 9
CH 1
CH 5
10
10
10
10
11
11
11
11
12
12
12
12
Appendix D, “TPU3
Freescale Semiconductor
13
13
13
CH 12
13
CH 8
CH 0
CH 4
14
14
14
14
LSB
LSB
15
15
LSB
15
LSB
15