MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1414

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Index-14
MIOS14SR0 interrupt status register 17-66
MIOS14SR1 interrupt status register 17-67
MIOS14TPCR test and signal control register 17-14
MIOS14TVECT vector register 17-14
MIOS14VNR module and version number
MISC counter register (MISCNT) 20-6
MISR High register 20-5
MISR Low register 20-5
MMCSM registers 17-22
MMCSMCNT MMCSM up-counter register 17-23
MMCSMML MMCSM modulus latch register 17-24
MMCSMSCR MMCSM status/control register 17-24
MMSCM status/control register duplicated
module configuration (QADC64E) 13-8
MPIOSMDDR MPIOSM data direction register 17-63
MPIOSMDR MPIOSM data register 17-62
MPWMCNTR MPWMSM counter register 17-58
MPWMPERR MPWMSM period register 17-57
MPWMPULR MPWMSM pulse width register 17-58
MPWMSCR MPWMSM status/control register 17-58
pads module configuration register (PDMCR) 2-22
pads module configuration register 2 (PDMCR2) 2-23
pending interrupt request register (UIPEND) 12-8
periodic interrupt status and control register
periodic interrupt timer count register (PITC) 6-45
periodic interrupt timer register (PITR) 6-45
PLL, low power, and reset control register
port A data register (PORTQA) 13-13
port B data register (PORTQB) 13-13
processor version register (PVR) 3-25
QACR0 control register 13-15
QADC64E control register 1 (QACR1) 13-15
QADC64E control register 2 (QACR2) 13-17
QADC64E module configuration (QADCMCR) 14-8
QADC64E PORTQA Port A data register 14-13
QADC64E PORTQA port A data register 13-13
READI data trace attribute 1 register (DTA1) 24-17
READI data trace attribute 2 register (DTA2) 24-17
READI development control register (DC) 24-10
READI device ID register (DID) 24-9
READI mode control register (MC) 24-11
READI ownership trace register (OTR) 24-8
READI read/write access register (RWA) 24-13
READI upload/download information register
READI user base address register (UBA) 24-12
real-time clock alarm register (RTCAL) 6-44
register 17-14
(MMCSMSCRD) 17-24
(PISCR) 6-44
(PLPRCR) 8-33
14-18
(UDI) 24-15
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14-14
MPC561/MPC563 Reference Manual, Rev. 1.2
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14-16
13-18
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real-time clock register (RTC) 6-43
real-time clock status and control register (RTCSC) 6-42
receive mask 16-7
reset status register (RSR) 7-5
SGPIO control register (SGPIOCR) 6-48
SGPIO data register 1 (SGPIODT1) 6-46
SGPIO data register 2 (SGPIODT2) 6-47
SIU interrupt edge level register (SIEL) 6-35
SIU interrupt mask registers (SIMASK) 6-33
SIU interrupt vector register (SIVEC) 6-35
SIU module configuration register (SIUMCR) 6-25
software service register (SWSR) 6-38
special purpose 3-44
status (QASR) 13-20
status (QASR0) 13-21
status (QASR1) 13-27
system clock and reset control register (SCCR) 8-30
system protection control register (SYPCR) 6-37
time base control and status register (TBSCR) 6-42
time base reference registers (TBREF0 and
time base SPR (TB) 3-23
time base SPR (TBSPR) 6-40
TOUCAN control register (CANCTRL0) 16-27
TOUCAN control register 0 (CANCTRL0) 16-27
TOUCAN control register 1 (CANCTRL1) 16-28
TOUCAN control register 2 (CANCTRL2) 16-30
TOUCAN error and status register (ESTAT) 16-33
TOUCAN error counters 16-36
TOUCAN free running timer (TIMER) 16-31
TOUCAN interrupt configuration register
TOUCAN interrupt flag register (IFLAG) 16-36
TOUCAN interrupt mask register (IMASK) 16-35
TOUCAN module configuration register
TOUCAN prescaler divide register (PRESDIV) 16-29
TOUCAN receive buffer 14 mask registers 16-32
TOUCAN receive buffer 15 mask registers 16-33
TOUCAN receive global mask registers 16-31
TPU channel interrupt enable register (CIER) 19-15
TPU channel interrupt status register (CISR) 19-19
TPU channel priority register (CPR) 19-18
TPU development support control register
TPU function select register (CFSR) 19-15
TPU host sequence register (HSQR) 19-16
TPU host service request register (HSRR) 19-17
TPU interrupt configuration register (TICR) 19-14
TPU module configuration register (TPUMCR) 19-11
added registers, 3-44
unsupported registers, 3-44
TBREF1) 6-41
(CANICR) 16-27
(CANMCR) 16-25
(DSCR) 19-12
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14-22
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14-22
14-28
Freescale Semiconductor