MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1005

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

24.7.7.2
Refer to
non-debug mode. The only difference between non-debug mode reset configuration and debug mode reset
configuration are the values of the DOR and DME fields in the DC register.
24.7.7.3
Refer to
24.7.7.4
If EVTI is negated at negation of RSTI, the READI module will be disabled. No trace output will be
provided, and output auxiliary signals will be three-stated. This is illustrated in
24.7.7.5
Freescale Semiconductor
•
•
•
System
Clock
RSTI
EVTI
An error message is sent out when an invalid TCODE is detected by the signal input formatter.
Refer to
An error message is sent out when an invalid access opcode is detected in auxiliary input messages
by the signal input formatter. Refer to
details.
If the TCODE is valid, then READI will expect that the correct number of packets have been
received and no further checking will be performed. If the number of packets received by READI
is not correct, READI response is not defined, unless the message is a download request message
(refer to
Section 24.7.7.1, “Reset Configuration for Debug
Section 24.2.2,
Reset configuration information must be valid on EVTI
at least 4 clocks prior to RSTI negation.
Reset Configuration for Non-Debug Mode
Secure Mode
Disabled Mode
Guidelines for Transmitting Input Messages
Section 24.10.8.2, “Invalid
Section 24.6.4, “Partial Register
“Security,” for further details.
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 24-18. READI Module Disabled
EVTI is sampled at the negation of RSTI. Since EVTI is
negated, the READI module is disabled.
Message,” for further details.
Section 24.10.8.3, “Invalid Access
Updates,” for further details).
Mode,” for details on reset configuration for
Figure
Opcode,” for further
24-18.
READI Module
24-37