MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1016

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

READI Module
24.8.4.2
Instruction fetches are snooped on the U-bus. There is a one-to-one correspondence between instruction
fetches marked with the U-bus program trace attribute and the indication of RCPU VF signal (only 3, 4,
5, and 6) between two synchronization events.
Since U-bus program trace attribute occurs after the indication of VF, it is latched and paired with the
nearest (previous) unpaired VF (3, 4, 5, and 6) indication to determine the instruction address.
For all other VF indications, except 3, 4, 5, and 6, it is not possible to determine the instruction address.
24.8.4.3
Instruction execution tracking is performed by capturing the RCPU VF and VFLS signals, and decoding
them to infer the state of the processor. The RCPU VF signals indicate two classifications of information:
24.8.4.4
The various conditions under which the RCPU may signal instruction flushes of the RCPU prefetch queue
or RCPU history buffer are:
24.8.5
READI implements a queue 16 or 32 messages deep (depending on the silicon version) for program trace,
data trace, and ownership trace messages. Messages that enter the queue are transmitted via the output
auxiliary port in the order in which they are queued.
24-48
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1. A taken branch (direct, indirect, interrupt or exception) will cause the instruction prefetch queue
2. A mispredicted branch will cause instructions fetched from the new stream to be flushed, and
3. An exception can cause cancellation of multiple taken branches which may require cancelling
The current instruction type which is being loaded into the RCPU instruction queue. For further
details refer to the RCPU Reference Manual.
The number of instructions which are currently being flushed from the RCPU instruction queue.
For further details refer to the RCPU Reference Manual.
(which contains instructions from the now old stream) to be flushed, and fetching will start from
the branch target stream. The sequential instruction count will be updated to reflect this.
fetching will resume from the old stream. It will also require a program trace message to be
cancelled and the trace to be corrected.
multiple program trace messages.
Branch Trace Message Queueing
Instruction Fetch Snooping
Instruction Execution Tracking
Instruction Flush Cases
If multiple trace messages need to be queued at the same time, program trace
messages will have the highest priority unless the data trace buffers are full,
in which case the data trace messages are given temporary higher priority
than the program trace messages.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
Freescale Semiconductor