MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 497

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

or write the result word table, but in normal operation, the software reads the result word table to obtain
analog conversions from the QADC64E. Unimplemented bits are read as zeros, and write operations do
not have any effect. See
While there is only one result word table, the data can be accessed in three different data formats:
The left justified, signed format corresponds to a half-scale, offset binary, two’s complement data format.
The data is routed onto the IMB3 according to the selected format. The address used to access the table
determines the data alignment format. All write operations to the result word table are right justified.
The three result data formats are produced by routing the RAM bits onto the data bus. The software
chooses among the three formats by reading the result at the memory address which produces the desired
data alignment.
The result word table is read/write accessible by software. During normal operation, application software
only needs to read the result table. Write operations to the table may occur during test or debug breakpoint
operation. When locations in the CCW table are not used by an application, software could use the
Freescale Semiconductor
1
SRESET
•
•
•
SRESET
SRESET
S = Sign bit.
Field
Addr
Right justified in the 16-bit word, with zeros in the higher order unused bits
Left justified, with the most significant bit inverted to form a sign bit, and zeros in the unused lower
order bits
Left justified, with zeros in the lower order unused bits
Field
Addr
Field
Addr
MSB
MSB
MSB
0
0
S
0
1
1
1
1
Figure 13-17. Right Justified, Unsigned Result Format (RJURR)
Figure 13-19. Left Justified, Unsigned Result Register (LJURR)
Figure 13-18. Left Justified, Signed Result Format (LJSRR)
Figure 13-17
2
0000_00
2
2
—
3
3
0x30 4B80–4BFF (LJURR_A); 0x30 4F80–4FFF (LJURR_B)
0x30 4A80–4AFF (RJURR_A); 0x30 4E80–4EFF (RJURR_B)
3
0x30 4B00–4B7F (LJSRR_A); 0x30 4F00–4F7F (LJSRR_B)
MPC561/MPC563 Reference Manual, Rev. 1.2
Undefined
RESULT
Undefined
4
4
4
for a diagram of the result word table
RESULT
5
5
5
6
6
6
7
7
7
8
8
8
9
9
9
Undefined
10
10
10
RESULT
11
11
11
QADC64E Legacy Mode Operation
12
00_0000
12
00_0000
12
—
—
13
13
13
14
14
14
LSB
LSB
15
LSB
15
15
13-33