MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 290

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Reset
If limp mode is enabled, the internal PLL is not required to be locked before the chip exits power-on reset.
The internal MODCK[1:3] values are sampled at the rising edge of PORESET. After exiting the power-on
reset state, the MPC561/MPC563 continues to drive the HRESET and SRESET pins for 512 system clock
cycles. When the timer expires (after 512 cycles), the configuration is sampled from data bus pins, if
required (see
HRESET and SRESET pins.
The PORESET pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. The
internal PORESET signal asserts only if the PORESET pin asserts for more than 100 ns.
7.1.2
HRESET (hard reset) is an active low, bidirectional I/O pin. The MPC561/MPC563 can detect an external
assertion of HRESET only if it occurs while the MPC561/MPC563 is not asserting HRESET.
When the MPC561/MPC563 detects assertion of the external HRESET pin or a cause to assert the internal
HRESET line is detected, the chip starts to drive the HRESET and SRESET for 512 cycles. When the timer
expires (after 512 cycles) the configuration is sampled from data pins (refer to
Configuration”) and the chip stops driving the HRESET and SRESET pins. An external pull-up resistor
should drive the HRESET and SRESET pins high. After detecting the negation of HRESET or SRESET,
the MPC561/MPC563 waits 16 clock cycles before testing the presence of an external hard or soft reset.
The HRESET pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. The internal
HRESET will be asserted only if HRESET is asserted for more than 100 ns.
The HRESET is an open collector type pin.
7.1.3
SRESET (soft reset) is an active low, bidirectional I/O pin. The MPC561/MPC563 can only detect an
external assertion of SRESET if it occurs while the MPC561/MPC563 is not asserting SRESET.
When the MPC561/MPC563 detects the assertion of external SRESET or a cause to assert the internal
SRESET line, the chip starts to drive the SRESET for 512 cycles. When the timer expires (after 512 cycles)
the debug port configuration is sampled from the DSDI and DSCK pins and the chip stops driving the
SRESET pin. An external pull-up resistor should drive the SRESET pin high. After the MPC561/MPC563
detects the negation of SRESET, it waits 16 clock cycles before testing the presence of an external soft
reset.
The SRESET is an open collector type pin.
7.1.4
devices use the MPC561/MPC563 input clock. Erroneous operation could also occur if devices with a PLL
7-2
If the PLL detects a loss of lock, erroneous external bus operation will occur if synchronous external
•
•
The Internal PLL enters the lock state and the system clock is active.
The PORESET pin is negated.
Hard Reset
Soft Reset
Loss of PLL Lock
Section 7.5.1, “Hard Reset
MPC561/MPC563 Reference Manual, Rev. 1.2
Configuration”) and the MPC561/MPC563 stops driving the
Section 7.5.1, “Hard Reset
Freescale Semiconductor