MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1056

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

IEEE 1149.1-Compliant Interface (JTAG)
The TAP consists of five dedicated signal pins, a 16-state TAP controller, and two test data registers. A
boundary scan register links all device signal pins into a single shift register. The test logic implemented
utilizes static logic design. The MPC561/MPC563 implementation provides the capability to:
25.1.1
An overview of the MPC561/MPC563 scan chain implementation is shown in
MPC561/MPC563 implementation includes a TAP controller, a 4-bit instruction register, and two test
registers (a one-bit bypass register and a 427-bit (MPC563) or 423-bit (MPC561) boundary scan register).
This implementation includes a dedicated TAP consisting of the following signals:
25-2
1. Perform boundary scan operations to test circuit-board electrical continuity.
2. Bypass the MPC561/MPC563 for a given circuit-board test by effectively reducing the boundary
3. Sample the MPC561/MPC563 system pins during operation and transparently shift out the result
4. Disable the output drive to pins during circuit-board testing.
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•
•
•
•
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scan register to a single cell.
in the boundary scan register.
TCK — a test clock input to synchronize the test logic. (with an internal pull-down resistor)
TMS — a test mode select input (with an internal pullup resistor) that is sampled on the rising edge
of TCK to sequence the TAP controller’s state machine.
TDI — a test data input (with an internal pullup resistor) that is sampled on the rising edge of TCK.
TDO — a three-state test data output that is actively driven in the shift-IR and shift-DR controller
states. TDO changes on the falling edge of TCK. (This pin also has a weak pull-up that is active
when output drivers are disabled, except during a HI-Z instruction).
TRST — an asynchronous reset with an internal pull-up resistor that provides initialization of the
TAP controller and other logic required by the standard. This input is multiplexed with the
PORESET signal.
JCOMP — JTAG Compliancy – This signal provides JTAG IEEE1149.1 compatibility and selects
between normal operation (low) and JTAG test mode (high).
Overview
Certain precautions must be observed to ensure that the IEEE 1149-like test
logic does not interfere with nontest operation. JCOMP must be low prior to
PORESET assertion after low power mode exits, otherwise an unknown
state will occur.
JTAG mode does not provide access to the internal MPC561/MPC563
circuitry. It allows access only to the input or output pad (periphery)
circuitry.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
NOTE
Figure
Freescale Semiconductor
25-2. The