MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 777

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
12:15
MDASM Control Register Bits
Bits
9:10
7:8
11
6
FORCB
MODE
Name
BSL
MODE
—
—
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
Force B bit — In the OCB, OCAB and OPWM modes, the FORCB bit allows the software to force
the output flip-flop to behave as if a successful comparison had occurred on channel B (except
that the FLAG line is not activated). Writing a one to FORCB resets the output flip-flop; writing a
zero to it has no effect.
In the DIS, IPWM, IPM and IC modes, the FORCB bit is not used and writing to it has no effect.
FORCB is cleared by reset and is always read as zero.
Writing a one to both FORCA and FORCB simultaneously resets the output flip-flop.
Reserved
Bus select bits — These bits are used to select which of the six 16-bit counter buses is used by
the MDASM. Each MDASM instance has four possible counter buses that may be connected.
See
NOTE: Unconnected counter buses inputs are grounded.
Reserved
Mode select bits — The four mode select bits select the mode of operation of the MDASM. To
avoid spurious interrupts, it is recommended that MDASM interrupts are disabled before
changing the operating mode.
The mode select bits are cleared by reset.
NOTE: The reserved modes should not be set; if these modes are set, the MDASM behavior is
undefined.
Table 17-21. MDASMSCR Bit Descriptions (continued)
Table 17-23
MPC561/MPC563 Reference Manual, Rev. 1.2
Resolution
Table 17-22. MDASM Mode Selects
Bits of
for more information.
—
16
16
16
16
16
—
—
16
15
14
13
12
11
Bus Bits
Counter
Ignored
0,1
0-2
0-3
0-4
—
—
—
—
—
—
—
—
—
0
Description
DIS – Disabled
IPWM – Input pulse width measurement
IPM – Input period measurement
IC – Input capture
OCB – Output compare, flag on B compare
OCAB – Output compare, flag on A and B compare
Reserved
Reserved
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
MDASM Mode of Operation
Modular Input/Output Subsystem (MIOS14)
17-45