MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 849

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

19.4.10 Channel Interrupt Status Register (CISR)
The channel interrupt status register (CISR) contains one interrupt status flag per channel. Time functions
specify via microcode when an interrupt flag is set. Setting a flag causes the TPU3 to make an interrupt
service request if the corresponding CIER bit is set. To clear a status flag, read CISR, then write a zero to
the appropriate bit.
19.4.11 TPU3 Module Configuration Register 2 (TPUMCR2)
Freescale Semiconductor
SRESET
SRESET
Bits
0:15
Bits
0:6
7
Field
Addr
Field CH
Addr
MSB
CH[15:0]
MSB
0
15
Name
Name
0
DIV2
CISR is the only TPU3 register that can be accessed on a byte basis.
—
1
CH
14
1
Figure 19-21. TPUMCR2 — TPU Module Configuration Register 2
Channel interrupt status
0 Channel interrupt not asserted
1 Channel interrupt asserted
Reserved
Divide by 2 control. When asserted, the DIV2 bit, along with the TCR1P bit and the PSCK bit in
the TPUMCR, determines the rate of the TCR1 counter in the TPU3. If set, the TCR1 counter
increments at a rate of two system clocks. If negated, TCR1 increments at the rate determined
by control bits in the TCR1P and PSCK fields.
0 TCR1 increments at rate determined by control bits in the TCR1P and PSCK fields of the
1 Causes TCR1 counter to increment at a rate of the system clock divided by two
2
TPUMCR register
CH
Figure 19-20. CISR — Channel Interrupt Status Register
13
2
—
3
CH
12
3
4
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 19-18. TPUMCR2 Bit Descriptions
Table 19-17. CISR Bit Descriptions
CH
11
5
4
0x30 4028 (TPU_A), 0x30 4428 (TPU_B)
0x30 4020 (TPU_A), 0x30 4420 (TPU_B)
6
CH
10
5
DIV2
CH 9 CH 8 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0
7
0000_0000_0000_0000
0000_0000_0000_0000
6
NOTE
SOFTRST
7
8
Description
Description
8
ETBANK
9
9
10
10
11
11
FPSCK
12
12
13
13
Time Processor Unit 3
T2CF DTPU
14
14
LSB
LSB
15
15
19-19