MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 416

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Memory Controller
Clock
Address
TS
No Effect, ACS = 00
TA
CS
RD/WR
WE/BE
OE
CSNT = 1
Data
Figure 10-14. Relaxed Timing — Write Access (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1
10.3.4
Extended Hold Time on Read Accesses
For devices that require a long disconnection time from the data bus on read accesses, the bit EHTR in the
corresponding OR register can be set. In this case any MPC561/MPC563 access to the external bus
following a read access to the referred memory bank is delayed by one clock cycle unless it is a read access
to the same bank.
Figure 10-15
through
Figure 10-18
show the effect of the EHTR bit on memory
controller timing.
Figure 10-15
shows a write access following a read access. Because EHTR = 0, no extra clock cycle is
inserted between memory cycles.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-18
Freescale Semiconductor