MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1127

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
0x30 5C00
0x30 5C04
0x30 5C06
0x30 5C08
1
2
0x30 501F
0x30 5020
0x30 5022
0x30 5024
0x30 5026
0x30 5028
0x30 502A
0x30 502C –
0x30 504A
0x30 504C –
0x30 506A
0x30 506C –
0x30 513F
0x30 5140 –
0x30 517F
0x30 5180 –
0x30 51BF
0x30 51C0 –
0x30 51DF
Address
Bits 0–3 writeable only in test mode, otherwise read only.
Bits 3–11 writeable only in test mode, otherwise read only.
Address
Table B-11. QSMCM (Queued Serial Multi-Channel Module) (continued)
Access
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
—
1
2
Table B-12. Peripheral Pin Multiplexing (PPM) Module
TX_CONFIG_1
TX_CONFIG_2
COMD.RAM
TRAN.RAM
QSCI1CR
PPMMCR
QSCI1SR
RECRAM
PPMPCR
SCC2R0
SCC2R1
Symbol
Symbol
SC2DR
SC2SR
MPC561/MPC563 Reference Manual, Rev. 1.2
SCRQ
SPSR
SCTQ
—
QSPI Status Register 3.
See
SCI2 Control Register 0.
See
SCI2 Control Register 1.
See
SCI2 Status Register.
See
SCI2 Data Register.
See
QSCI1 Control Register.
See
QSCI1 Status Register.
See
Transmit Queue Locations
Receive Queue Locations
Reserved
Receive Data RAM
Transmit Data RAM
Command RAM
PPM Module Configuration Register
See
PPM Contol Register
See
Transmit Configuration Register 1
See
Transmit Configuration Register 2
See
Table 15-18
Table 15-24
Table 15-25
Table 15-26
Table 15-27
Table 15-32
Table 15-33
Table 18-2
Table 18-3
Table 18-6
Table 18-6
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for channel settings.
for channel settings.
Register
Register
Size
16
16
16
16
16
16
16
16
—
16
16
16
8
Size
Internal Memory Map
16
16
16
16
Reset
Reset
—
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
B-17