MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1153

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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Appendix D
TPU3 ROM Functions
The following pages provide brief descriptions of the pre-programmed functions in the TPU3. For detailed
descriptions, refer to the programming note for the individual function. The Freescale TPU Literature
Pack provides a list of available programming notes.
D.1
The TPU3 contains 4 Kbytes of microcode ROM. It can have up to 8 Kbytes of memory and a maximum
of four entry tables (see
MPC561/MPC563.
The TPU3 can address up to 8 Kbytes of memory at any one time. It has 4 Kbytes of internal ROM, located
in banks 0 and 1, and 8 Kbytes of dual-ported SRAM (DPTRAM), located in banks 0, 1, 2, and 3. As only
one type of memory can be used at a time, the TPU3 must either use the internal ROM or the SRAM.
Functions from both memory types cannot be used in conjunction.
A new feature of the TPU3 microcode ROM is the two 16-function entry tables in the 4 Kbytes of internal
ROM. The ETBANK field in the TPUMCR2 register, written once after reset, determines which one of
Freescale Semiconductor
1
Overview
The DPTRAM is located at 0x30 2000.
Add - Entry
Add - Entry
Add - Entry
TPU3ROM
Add-Entry
Code
Code
Entry
Code
Code
Figure
D-1). This appendix defines the standard ROM functions for the
MPC561/MPC563 Reference Manual, Rev. 1.2
7 FF
0
1FF
3 FF
Figure D-1. TPU3 Memory Map
Add - Entry
Add - Entry
Add - Entry
DPTRAM
.
Code
Entry
Code
Code
Code
1
1FF
3 FF
7 FF
0
5 FF
D-1

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