MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1373

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

G.22 MPIOSM Timing Characteristics
Note: All delays are in system clock periods.
Freescale Semiconductor
1
2
MPIOSM input pin period
MPIOSM pin low time
MPIOSM pin high time
Input pin to MPIOSM_DR delay
Output pulse width
MDASM interrupt flag
The minimum input pin period, pin low and pin high times depend on the rate at which the MPIOSM_DR
register is polled.
The minimum output pulse width depends on how quickly the CPU updates the value inside the MIOPSM_DR
register.
Counter bus[15:0]
MDASMAR[15:0]
MPIOSM input pins
Figure G-62. MPIOSM Input Pin to MPIOSM_DR (Data Register) Timing Diagram
Figure G-61. Counter Bus to MDASM Interrupt Flag Setting Timing Diagram
MPIOSM_DR
Characteristic
f
SYS
2
f
SYS
5AFC
5AFE
Table G-27. MPIOSM Timing Characteristics
MPC561/MPC563 Reference Manual, Rev. 1.2
FFA5
5AFD
FFA5
t
Output mode
PDR
Input Mode
Symbol
t
t
t
PULW
PPER
t
t
PLO
PDR
PHI
005A
005A
t
5AFE
CBFLG
Min
—
—
—
—
0
1
1
1
2
66-MHz Electrical Characteristics
Max
—
—
—
—
1
G-67