MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 320

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Clocks and Power Control
The return to normal-high mode from normal-low, doze-high, low, and sleep mode is accomplished with
the asynchronous interrupt. The sources of the asynchronous interrupt are:
The system responds quickly to asynchronous interrupts. The wake-up time from normal-low, doze-high,
doze-low, and sleep mode caused by an asynchronous interrupt or a decrementer exception is only three
to four clock cycles of maximum system frequency. In 40-MHz systems, this wake-up requires 75 to 100
ns. The asynchronous wake-up interrupt from the interrupt controller is level sensitive one. It will therefore
be negated only after the reset of interrupt cause in the interrupt controller.
The timers’ (RTC, PIT, time base, or decrementer) interrupts indications set status bits in the PLPRCR
(TMIST). The clock module considers this interrupt to be pending asynchronous interrupt as long as the
TMIST is set. The TMIST status bit should be cleared before entering any low-power mode.
Table 8-7
8.7.3.1
In normal mode (as well as doze mode), if the PLPRCR[CSRC] bit is set, the system toggles between low
frequency (defined by PLPRCR[DFNL]) and high frequency (defined by PLPRCR[DFNH]. The system
switches from normal-low mode to normal-high mode if either of the following conditions is met:
When neither of these conditions are met, the PLPRCR[CSRC] bit is set, and the asynchronous interrupt
status bits are reset, the system returns to normal-low mode.
8-18
•
•
•
•
•
Asynchronous wake-up interrupt from the interrupt controller
RTC, PIT, or time base interrupts (if enabled)
Decrementer exception
An interrupt is pending from the interrupt controller; or
The MSR[POW] bit is cleared (power management is disabled).
summarizes wake-up operation for each of the low-power modes.
Exiting from Normal-Low Mode
Normal-low (“gear”)
Operation Mode
Power-down
Deep-sleep
IRAMSTBY
Doze-high
Doze-low
Sleep
Table 8-6. Power Mode Wake-Up Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
Wake-up
Software
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
External
Method
or
< 500 oscillator cycles + power
Return Time from Wake-up
3-4 maximum system cycles
3-4 maximum system clocks
Asynchronous interrupts:
3-4 actual system cycles
Synchronous interrupts:
Event to Normal-High
< 500 Oscillator Cycles
Power-on sequence
125 µs – 4 MHz
25 µs – 20 MHz
supply wake-up
Freescale Semiconductor